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ASMC back in Boston

The IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC) returns to Boston May 22–24 with a full docket of technical presentations as well as morning keynotes from Texas Instruments, TSMC, and The Nanotechnology Group. This year’s event, which adjourns at the Sheraton Hotel in Boston’s Back Bay area, features 14 conference and poster sessions. Topics include metrology, APC, yield enhancement, defect inspection, lithography, productivity, factory dynamics and automation, and advanced processes and materials.

A special overview session focusing on the new International Technology Roadmap for Semiconductors convenes the morning of May 23, while that afternoon an industry panel will discuss ideas on how to maintain the productivity curve and debate the necessity of a move to larger wafer size. (Disclaimer: MICRO is a media sponsor of ASMC, and editor Tom Cheyney will moderate the panel.)

The May 22 keynote, “Nanotechnology: What Is It and How Does It Apply to Me in Semiconductor Manufacturing,” will be presented by noted nano expert and author, Deb Newberry. Continuing on the theme of the growing connection between nanotech and chipmaking, the May 23 keynote from Chenming Hu of TSMC and UC Berkeley is titled “From CMOS to NanoCMOS.” Venu Menon, vice president and CMOS1 manager in TI’s silicon technology development group, will deliver a May 24 morning address incorporating some of his recent production-ramp experiences, “Challenges and Opportunities for Volume Manufacturing at 65 nm and Beyond.”

An interactive poster session and reception featuring more than 25 presentations takes place the evening of May 22. In addition to the conference lineup, two SEMI standards seminars on equipment data acquisition (Interface-A) and SECS/GEM/ GEM300 factory automation immediately follow the conclusion of the main event on May 24–25. For more information on ASMC 2006, check

TSMC readies immersion

Saying its immersion lithography program had processed test wafers well within acceptable parameters for volume manufacturing, TSMC continues to target 45 nm as the insertion point for the wet technique into production. In papers presented at the recent SPIE Microlithography conference in San Jose, company R&D researchers showed the results of a proprietary scheme designed to reduce bubbles, watermarks, particles, resist residue, and other immersion-related defects. Their data revealed as few as three defects per 300-mm wafer (or 0.006/cm2), with an average of seven defects over the range of test wafers (or 0.014/cm2).

“Recently, TSMC produced multiple test wafers with defect rates…better than any other immersion results to date and comparable to the very best dry lithography results,” said Burn Lin, senior director of the company’s micropatterning division. “With defect root causes understood, TSMC can now focus on throughput improvement for high-volume manufacturing.”

Spintronics program started

Four California universities have joined forces to launch a joint research program on spintronics, the Western Institute of Nanoelectronics. The participating schools are Stanford University and three University of California campuses: Berkeley, Los Angeles, and Santa Barbara. UCLA’s Henry Samueli School of Engineering and Applied Science will host the administrative headquarters, with scientific and technical responsibilities shared among the participants.
An initial grant of $18.2 million will be distributed over a four-year period. Six chipmakers—AMD, Freescale, IBM, Intel, Micron, and Texas Instruments—contributed $2.38 million in the form of a Nanoelectronics Research Initiative grant, with Intel offering another $2 million and a separate equipment donation of $10 million.

Infrastructure and personnel support from the participating universities is expected to exceed $200 million. The semiconductor industry sponsors and four schools will comanage the program, with 10 chipmaker researchers working alongside students and faculty on all of the campuses. A total of 30 researchers will participate in the interdisciplinary projects, which will investigate ways to harness the spin of electrons to carry information and minimize power consumption.

“Today’s devices, which are based on CMOS, can’t get much smaller and still function properly and effectively,” said Kang Wang, a UCLA professor and director of the new institute. “That’s where spintronics comes in.”

SEMI issues standards

Fourteen new technical standards have been published by SEMI and its international standards program. The new standards include a method of determining particle contamination from minienvironments, a specification for job deck data format for variable-shaped beam photomask writers, a guide to specifying wafer–wafer bonding alignment targets, a spec for SECS II protocols for substrate mapping, and a provisional spec for XML messaging for process control systems. Several compound semiconductor– related standards are among the new issues, such as specifications for sapphire substrates for compound epi wafers and round 200-mm polished monocrystalline GaAs wafers. For more information on these and the more than 720 other SEMI standards, go to

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