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Transistorama

Optimizing the poly1 doping process to reduce deep-trench resistance and leakage

Min-Soo Kim, William Cooper, Brian Simonson, David Ricks,
Eric McDaniel, Roderick Miller, Richard Chapman, Thomas Taylor,
and Robert Fuller, Infineon Technologies

Modern CMOS manufacturing processes, including those used to fabricate DRAM devices, generally use doped polysilicon as a conducting material.1,2 Another process that uses arsenic-doped polysilicon as a capacitor electrode to form a capacitor is deep-trench technology.3 Doped polysilicon resistance and leakage current through node dielectrics play a dominant role in preventing retention loss and maintaining signal margin in DRAM products. As design rules shrink below 110 nm, it has become more challenging to ensure lower resistance and lower leakage current through the node in the trench, which are necessary to ensure proper device operation.4

This article describes the influence of arsenic-doped polysilicon on the signal margin and node leakage current in 110-nm deep-trench DRAM products. Methods for optimizing both the physical and electrical qualities of polysilicon are presented, and the challenge of performing electrical characterization quickly to achieve rapid yield learning for a new process are discussed. Finally, how these methods can be applied to other poly layers and to next-generation devices is discussed briefly.

Bit Line Coupling and Trench-Node Leakage

During the development of doped polysilicon recipes using a vertical low-pressure chemical vapor deposition (LPCVD) furnace at Infineon Technologies’ 300-mm fab in Richmond, VA, it was observed that poly doping performance and its impact on product yields vary with the number and position of wafers loaded into the furnace. When furnace loading was increased from one to four lots, the DRAM product that was processed at the bottom center and bottom of the furnace was affected by bit line coupling (BLC) loss, as illustrated in Figure 1. Physical failure analysis showed that material with higher resistance and amorphous nodules were present in the deep trenches, as shown in Figure 2.

Figure 1: When a total of four wafer lots were run in the LPCVD furnace, DRAM product that was processed at the bottom center and bottom of the furnace was affected by bit line coupling loss.

First, engineers searched for in-line data to explain these observations. However, there was no easy way to determine the root cause of the problem using in-line sheet resistance (Rs) and thickness monitoring data. Second, the engineers tried to access electrical data, but almost all of the electrical parameters had been filtered out. Hence, proper electrical characterization could not be performed.

Figure 2: Image showing that material with higher resistance and amorphous nodules was present in the deep trenches of DRAM products on wafers that were processed at the bottom center and bottom of the LPCVD furnace.

When the furnace loading size was reduced from four to two lots to avoid BLC loss, the product that was run at the bottom center and bottom of the furnace was affected by higher trench-node leakage (VPLL), which subsequently caused retention loss, as illustrated in Figure 3. Although the sharp transition between good and bad wafers was similar for the BLC loss shown in Figure 1 and the VPLL loss shown in Figure 3, multiple physical failure analyses were unable to generate enough data to uncover the root cause of the yield problem.

Figure 3: When a total of two wafer lots were run in the furnace, DRAM product that was run at the bottom center and bottom of the furnace was affected by higher trench-node leakage, which subsequently caused retention loss.

To resolve the yield issue, two process changes were considered. One was to optimize arsenic concentration, while the other was to optimize the uniformity of the first undoped layer on all the wafers in the boat. The results of these changes were analyzed using secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), and short-flow electrical product wafers. These methods achieved results 10 times faster than by using full-flow product wafers.

Optimizing the Doped Poly Process

Arsenic Flow Optimization. An investigation of the poly process showed that while arsenic flowed into the LPCVD furnace through two side injectors, it did not flow through the bottom injector. Although it is well understood that arsenic doping is a highly self-limiting process, the engineers routed arsenic flow through all three injectors, including the bottom one, and increased doping time to achieve complete arsenic saturation throughout the furnace. Since the engineers were interested in rectifying yield losses in wafers near or at the bottom of the furnace, they used the bottom injector to supply 66.7% of the total arsenic gas and the two side injectors to supply equal amounts of the remaining gas.

Since Rs and thickness data are not sufficient to characterize how changes in the poly process affect fully processed DRAM product, both physical and pseudoelectrical analyses were adopted to characterize the arsenic-injection and doping-time modifications.

First, the investigators performed a cross-sectional analysis on productlike wafers to determine whether amorphous nodules were still present in the trench after the arsenic modification. The results of that physical failure analysis, presented in Figure 4, confirmed that as a result of changing the arsenic injection into the furnace, there were no amorphous nodules such as those illustrated in Figure 2.

Figure 4: Cross-sectional views from productlike wafers processed (a) at the top and (b) at the bottom of the furnace confirmed that after the arsenic-injection modification, there were no amorphous nodules such as those illustrated in Figure 2.

Then the investigators verified the amount of arsenic in the trenches to ensure proper device operation. For this purpose, SIMS analysis was performed on test wafers that had been run with real product wafers. As shown in Figure 5, the SIMS analysis determined the arsenic peak values for wafers that had been placed in the bottom, middle, and top positions of the wafer boat and the amount of arsenic in the trenches (the area in the chart below the curves). Based on this analysis, the investigators concluded that product signal margin performance had apparently not been affected.

Figure 5: SIMS analysis showing the arsenic peak values for wafers that had been placed in the bottom, middle, and top positions of the wafer boat and the amount of arsenic in the trenches (the area in the chart below the curves).

Following physical failure analysis and pseudoelectrical analysis, it was decided to change the process of record (POR) to resolve the massive BLC yield loss. The new POR changed the amount of arsenic flow through the bottom of the furnace. As a result, fully processed DRAM product processed using the POR showed no BLC loss, as was expected.

However, because of higher VPLL loss, the product still suffered from retention loss, as illustrated in Figure 6.

Figure 6: After arsenic flow through the bottom of the furnace was modified, BLC loss was eliminated, but VPLL loss remained, leading to retention loss.

Electrical investigation of lots with VPLL yield loss showed that dramatic failures were dependent on furnace loading position. In addition, the VPLL yield loss correlated with polysilicon accumulation ratio changes, which also depended on furnace loading position, as shown in Figure 7.

Figure 7: Electrical investigation showing (a) that VPLL yield loss was dependent on furnace loading position, and (b) that the VPLL yield loss correlated with polysilicon accumulation ratio changes, which also depended on furnace loading position.

The investigators observed that the VPLL yield-loss problem was confined to the bottommost 5–10 wafers in the furnace and that the actual yield impact was random. While there was virtually no yield loss in some lots, the loss in others was very severe. Hence, site-specific physical failure analysis was performed using TEM. The TEM results, shown in Figure 8, revealed the presence of a compromised nitride/oxide dielectric layer that was caused by very small amorphous nodules. After discovering the compromised node integrity, the engineers performed a component-level yield investigation to determine the product’s long-term reliability. It was concluded that prefuse test coverage was robust enough to filter out chips with compromised node integrity.

Figure 8: TEM results from site-specific physical failure analysis revealed the presence of a compromised nitride/oxide dielectric layer that was caused by very small amorphous nodules.

Silane Flow Optimization. A SEM analysis of the new poly POR, in which the process was stopped right before the arsenic gas was turned on, revealed undoped-layer thickness variations on wafers at different furnace boat positions, as shown in Figure 9. Because surface morphology variations made it impossible to capture actual thickness data, thickness was determined by the density and size of the hemispherically grained silicon. This investigation indicated that wafers in the bottommost furnace zone had the thickest silicon film.

Figure 9: SEM analysis of the new poly POR in which the process was stopped right before the arsenic gas was turned on, revealing undoped-layer thickness variations on wafers at different furnace boat positions.

Based on the cross-sectional information derived from the images in Figure 9, the silane injection method was changed by installing two side injectors, one toward the top and one toward the bottom of the furnace. It is well known that multiple injectors improve furnace zone-to-zone thickness uniformity. Each of the new injectors had 10 holes to ensure even gas distribution. Consequently, while 54.6% of the total silane gas flowed through the upper side injector, 45.4% flowed through the bottom side injector to compensate for gas depletion from the upper part of the furnace.

To fully characterize the new process, all in-line parameters, including Rs and thickness, were characterized using SEM, SIMS, and other analysis methods. However, in the absence of real electrical parameters, which could be obtained only after the full process had been completed, the effect of the POR change could not be determined quickly.

Rapid Electrical Characterization of the Process Change

The investigators suspected that the VPLL yield loss was related not only to doping in the trenches but also to how silicon crystallized after subsequent thermal deposition steps. However, the impact of the yield loss on the product could be checked only by performing electrical tests on a fully processed lot. Hence, it was essential to develop a quick electrical characterization method to realize the potential yield benefit of the new process.

To shorten the very long electrical evaluation times, the engineers used an existing photomask that had been designed to define a capacitor test structure after poly2 deposition. Using this method, a test of capacitor value at 0 and 1 V was performed using a standard capacitance-voltage (CV) analysis to calculate the poly accumulation factor and a standard current voltage (IV) measurement to determine node leakage current at half of the operating voltage. The poly accumulation value from the CV measurement was used to determine the yield impact of the new POR on the fully processed product. The accumulation value obtained using this method is shown in Figure 10.

Figure 10: Poly accumulation value derived from the CV measurement, which was used to determine the yield impact of the new POR on the fully processed product.

After the new characterization method was implemented, overall electrical testing time was reduced from approximately 60 days to a week. Based on the electrical data generated using the new characterization method, the POR could be changed quickly. As a result, both BLC and VPLL yield losses have been eliminated.

Conclusion

This article has shown how BLC and VPLL yield loss in DRAM products was caused by a nonoptimized poly1 process. The yield loss was addressed successfully and eliminated by optimizing both the physical and electrical qualities of the polysilicon.

The effort to optimize arsenic flow to eliminate BLC yield loss demonstrated that when there is not enough dopant in the polysilicon, the polysilicon behaves like a high-resistive wire. As a result, the signal margin between 0 and 1 in the DRAM cell falls below the sensitivity of the sense amplifier. In this case, the overall DRAM yield loss appeared as a BLC loss. Optimizing silane flow to eliminate VPLL yield loss showed that not only the level of total dopants in the polysilicon, but also the level of electrically active dopants, is important to ensure the conducting nature of polysilicon.

It was not possible to uncover the root cause of the amorphous nodules that compromised node/oxide integrity. Presumably, nodule formation is related to the phase transition from amorphous to polycrystalline silicon during the thermal processing steps that take place after poly1 deposition. If so, it can be concluded that VPLL loss is caused by the compromised node/oxide integrity, which provides a leakage path and a higher-resistive polysilicon wire, effectively applying higher voltage to the capacitor electrode. To ensure proper device operations in the future, efforts should be made to understand the physical and electrical nature of polysilicon in smaller geometries.

Deep-trench technology uses very deep trenches to make a DRAM capacitor. In the POR flow, the trench-loading effect, which fills the trench for the first time, is most observable in the poly1 layer. While a similar trench-loading effect should be expected on subsequent poly layers, it is far less prevalent than on the poly1 layer.

Investigation in a stable high-volume yield environment detected a small electrical parameter variation between the poly1 layer and subsequent poly layers that was observed across wafers that had been processed at different positions in the furnace. The variation did not cause yield loss.

However, even when yield loss is not an issue, it is necessary to extend poly learning to other layers to ensure a more-stable and robust yield learning foundation. Furthermore, next-generation deep-trench technology should be developed so that on-product thickness matching and the productlike physical and electrical characterization of critical processes can be performed.

Acknowledgments

This article is an edited version of a paper that will be presented at the IEEE/SEMI Advanced Semiconductor Manufacturing Conference, to be held May 22–24 in Boston. The authors would like to thank Wilhelm Claussen, Deshawn Chapman, Heather Klesat, Kevin Snead, Althoff Klaus, David Robey, Juergen Daleiden, Konrad Semmler, and everyone at Infineon who was involved in the challenge of the new 300-mm factory start-up and ramp-up.

References

1. T Kamins, Polycrystalline Silicon for Integrated Circuits and Displays, 2nd ed. (Norwell, MA: Kluwer Academic Publishers, 1998).

2. S Wolf and RN Tauber, Silicon Processing for the VLSI Era, vol. 1 (Sunset Beach, CA: Lattice, 1995).

3. E Adler et al., “The Evolution of IBM CMOS DRAM Technology,” IBM Journal of Research and Development 39, no. 12 (1995): 167–188.

4. JA Mandelman et al., “Challenges and Future Directions for the Scaling of Dynamic Random-Access Memory (DRAM),” IBM Journal of Research and Development 46, no. 2/3 (2002): 187–212.


Min-Soo Kim is a process integration engineer who focuses on 300-mm deep-trench front-end-of-line integration at Infineon Technologies in Richmond, VA. With more than 10 years of experience as a diffusion process and process integration engineer, he has worked on SRAM, flash, and DRAM technologies. He received BS and MS degrees in physics from Sogang University, Seoul, South Korea. (Kim can be reached at 804/952-8755 or min-soo.kim@infineon.com.)

William Cooper is a process engineer who focuses on 300-mm deep-trench arsenic-doped amorphous and crystalline poly at Infineon Technologies. With five years of experience as a diffusion process engineer, he has worked on flash and DRAM technologies. He received a BS in chemical engineering from Pennsylvania State University in University Park. (Cooper can be reached at 804/952-8742 or william.cooper@infineon.com.)

Brian Simonson is a product engineer for the 300-mm wafer start-up and ramp of 110-nm technology at Infineon Technologies. He has eight years of product engineering experience in the semiconductor industry, primarily in the area of wafer yield analysis. He received a BS in electrical engineering from Old Dominion University in Norfolk, VA. (Simonson can be reached at 804/952-7098 or brian.simonson@infineon.com.)

David Ricks is a TEM engineer at Infineon Technologies. He has more than 15 years of semiconductor analytical experience and has expertise in the areas of SIMS, TEM, Auger, and SEM analysis. He received BS degrees in physics and mathematics and an MS in materials science and engineering from North Carolina State University in Raleigh. (Ricks can be reached at 804/952-7066 or david.ricks@infineon.com.)

Eric McDaniel, PhD, is a failure-analysis engineer at Infineon Technologies. He has 10 years of materials characterization and semiconductor failure-analysis experience. He received a BS in physics from West Virginia University in Morgantown and a PhD in physics from the University of Virginia in Charlottesville. (McDaniel can be reached at 804/952-7140 or eric.mcdaniel@infineon.com.)

Roderick Miller is lead 110-nm device engineer at Infineon Technologies’ 300-mm fab. He has more than 15 years of experience in device and product engineering for ASIC, EEPROM, SRAM, and DRAM products. He received BS and MS degrees in electrical engineering from North Carolina State University in Raleigh. (Miller can be reached at 804/952-7392 or roderick.miller@infineon.com.)

Richard Chapman is lead product engineer for consumer and mobile products at Infineon Technologies. He has 20 years of experience in the semiconductor industry in the areas of R&D, quality, and manufacturing. Chapman has written more than 10 publications on subjects ranging from electronic material nanostructures to manufacturing principles. He received an MS in material science and engineering from North Carolina State University in Raleigh. (Chapman can be reached at 804/952-7309 or richard.chapman@infineon.com.)

Thomas Taylor is the technology/yield coordinator for commodity DRAM products at Infineon Technologies’ 300-mm fab. He has 20 years of experience in the semiconductor industry in the areas of R&D, design, and manufacturing. Taylor has authored or coauthored more than 10 publications dealing with design, product, and yield analysis. He also holds six patents related to semiconductors or semiconductor analysis. He received an MS in electrical engineering from Clemson University in Clemson, SC. (Taylor can be reached at 804/952-7916 or thomas.taylor@infineon.com.)

Robert Fuller is lead integration engineer at Infineon Technologies’ 300-mm fab. He has been with the company since the 200-mm fab start-up nine years ago and has 26 years of semiconductor experience. Fuller holds 12 patents in various semiconductor fields. He received an MS in physics from North Carolina State University in Raleigh. (Fuller can be reached at 804/952-7928 or robert.fuller@infineon.com.)


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