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Defect/Yield Analysis and Metrology

Implementing automated defect inspection to enhance foundry yields

Janet Goh Pau Ying, 1st Silicon; and Shuba Chandar and Tan Chang Ou, Rudolph Technologies

In the competitive semiconductor environment, manufacturers must be able to ramp new processes quickly and maintain high yields during production. Fast ramp-up and high yields are especially critical for foundries, which manufacture a greater variety of products with shorter production runs than traditional IDMs. When device runs are limited, even relatively short-lived ramp problems or process excursions can reduce revenues significantly or even result in losses.

In contrast to many semiconductor manufacturing process steps, the lithography area provides a unique opportunity to recover yields when defects are detected in time. This article describes the implementation of automated macrodefect inspection at 1st Silicon’s fab in Kuching, Sarawak, Malaysia. The work was performed using a WaferView inspection and review system from Rudolph Technologies (Flanders, NJ), which successfully monitored the performance of the photolithography process.

Detecting Litho-Related Defects

In general, the lithography process consists of three primary steps: spinning on the photoresist material, exposing the photoresist to light through a mask containing the desired pattern, and developing the photoresist, which involves removing unwanted material to replicate the mask pattern in the photoresist.

Defects can occur during each of these process steps. Resist splatters, resist flares, nonuniform resist, splashback, develop drips, scumming, scratches, particles, and hot spots are all typical defects. Other examples are lack of resist coating, lack of pattern formation, nonexposure, pattern collapse, the printing of wrong patterns, wafer defocus, improper overlay alignment, and nondevelopment. Although the frequency of lithography defects is low, wafers must pass through the lithography processes at least once for every layer in the device, increasing the cumulative probability of yield-robbing defects.

However, if a defect in the resist pattern is detected before the pattern is transferred to the underlying layer through a nonreworkable process such as etch, it can be corrected by simply removing the resist and repeating the lithography step. The correctable nature of lithography defects makes their detection particularly valuable. Whereas the presence of noncorrectable defects compels manufacturers to diagnose and correct defect excursions and prevent future yield loss, the detection of correctable defects potentially enables them to recover prior process investment.

The high value of detecting and correcting lithography defects argues in favor of 100% inspection of every wafer every time it completes a lithography cycle. However, total inspection using conventional human-based inspection techniques is neither technically feasible nor economically justifiable. Human inspection is relatively slow, requiring several people to equal the throughput of a typical lithography process. Compounding the expense of multiple inspectors is their inherent subjectivity, which unavoidably lowers detection consistency, especially as the number of inspectors increases. Consequently, manufacturers historically have settled for inspecting only a fraction of the wafers processed, often less than 15%.

This limited sample severely restricts their ability to detect random defects and increases the average time to detect systematic defects. The additional time required to detect defects increases the number of misprocessed wafers that must be scrapped as a result of process excursions.

The introduction of high-throughput automated defect inspection technology has made 100% inspection both technically and economically feasible. Current-generation systems offer throughputs in excess of 100 wafers per hour, which is sufficient to keep pace with most lithography processes. Furthermore, automated defect classification eliminates the subjectivity factor, which results in inconsistencies stemming from widely varying defect sizes and appearances and the presence of defects that have the same root cause but look different at different processing levels.

In addition, providing a clear set of classification rules and training operators to apply them correctly has been challenging. A study has shown that while human inspectors accurately classified defects only 55% of the time before undergoing training, a disciplined training regime improved accuracy to 80%. Meanwhile, sophisticated automated classification algorithms can achieve 90% or better classification accuracy. Automated systems’ improved defect classification enables engineers to isolate process problems more quickly and provides more-useful data for statistical process control.

The adoption of automated defect inspection has also been driven by the industry shift to 300-mm wafers. First, 300-mm wafers have more than double the area and number of die of their 200-mm predecessors, making them more valuable than the smaller substrates. Second, virtually all manual handling has been eliminated in advanced 300-mm fabs, an application of the lights-out concept.

Defect Inspection and Classification Technology

All inspection systems inspect the full wafer by acquiring a number of smaller images that are subsequently stitched together to form a full wafer image. At the same time, all systems must make a trade-off between resolution and throughput. There are optical limitations that determine the resolution available through a given lens system at a given field size. There are also sensor and data processing limitations that affect the resolution/throughput trade-off. In general, throughput can be expected to decrease with the square of resolution. In practice, engineers often optimize this trade-off by inspecting the entire wafer at a somewhat lower resolution and then directing selected defects to a high-resolution review station for additional characterization.

Defect detection is most effective if it is based on all available data, including from full-color bright-field imaging and dark-field imaging. Bright-field images resemble the types of images that are observed by human inspectors using reflected light at near-normal incidence. Dark-field images, which are created using grazing-incidence illumination, consist of bright features against a dark field that are generated when light is scattered by raised features such as particles.

Macrodefects. As the name implies, macrodefects were originally those that were visible to the unaided human eye. Although human vision is limited in its resolving power to about 0.2 mm, defects much smaller than that could be detected by the light they scatter under intense illumination. Inspectors eventually came to use optical microscopes to characterize defects that they detected visually. Hence, the definition of macrodefects has expanded to include defects much smaller than the resolution of the human eye.

Automated macrodefect inspection systems employ optical microscopes and can detect defects as small as a few micrometers. Macrodefects range in size from those that are much larger than the minimum feature size of the semiconductor device to those that are as large as the entire wafer.

Local versus Global Defects. Defects fall broadly into two categories: local and global. Local defects are typically much smaller than the die and include particles and isolated scratches, as illustrated in Figure 1. They are most effectively detected using die-to-die image comparisons. A simple subtraction of two properly aligned images results in the rapid identification of pixels that differ between them. The images are then processed for continuity to identify those pixels that correspond to a single defect. Further processing can identify features such as isolated scratches, which consist of linearly aligned discrepant pixels. Generally, local defects contain sufficient pixels to permit classification but not to resolve imaging fully. Local defects can be classified in real time as each individual image is acquired.

Figure 1: Six types of defects that are known to contribute significantly to yield loss include (a) color variations, (b) particles, (c) scratches, (d) defocus, (e) coating defects, and (f) poor exposure. These defects were initially targeted for detection and reduction using automated defect inspection.

Global defects require additional processing, which cannot begin until imaging of the full wafer is completed. First, the individual images must be stitched together to form a full wafer image. Then the defective areas are grouped together and the groups are subjected to spatial signature analysis. Other techniques are also useful. For example, histogram analysis, which plots the number of pixels at each intensity level for each color channel (red, green, and blue) is particularly effective in detecting global color defects. The gradual changes often associated with global defects make them difficult to detect using die-to-die comparisons.

Defect Inspection System Features

Color Detection and Correction. The use of color provides critical information in the inspection process. Many defects such as missing layers and film-thickness variations, which are difficult to distinguish using broadband illumination and gray-scale methods, can be seen using color detection. While early color detection techniques compared an image with a reference frame from a “golden” standard image, that approach is prone to false positives because of inherent variations in wafer color that do not necessarily indicate the presence of defects. Color-correction algorithms address that problem by comparing the color parameters acquired from the current wafer with a constantly updated reference calculated from previously inspected wafers using the same inspection recipe.

An example of color correction is presented in Figure 2. Without color correction, the inspection system identified a large number of local color defects all over the wafer, as shown in Figure 2a. However, with color correction, the actual failure mode, uneven topography across the wafer, and the resulting defect area could be correctly identified, as shown in Figure 2b. Full-color imaging was able to detect this defect, and color correction could classify it properly and incorporate it accurately into the statistical process control database.

Figure 2: Image from the inspection system without color correction (a) shows many local color defects all over the wafer. Image from the system with color correction (b) shows correct identification of uneven topography across the wafer and the resulting defect area.

Knowledge Base. Many automated defect classification systems provide a limited number of fixed defect classifications. That inflexibility limits the tools’ utility in real-world applications, which abound in hundreds of distinguishable defect types. Advanced systems employ a knowledge-base approach that permits users to define new defect categories based on as few as three to five representative images of the defect.

A knowledge base is a collection of correctly classified samples that are stored in an n-dimensional matrix (n is the number of descriptors). The samples are broken down by rules that uniquely describe specific types of defect classes. The matrix includes class-rule descriptors, which are stored as vectors, and the name of the defect class, such as particle, scratch, wrong reticle, no develop, etc. Once the defect image has been isolated, the classification process can begin. The image is broken down into a set of mathematical descriptors that denote attributes such as size, intensity, and edge sharpness. The set of descriptors for a particular image is then compared against the knowledge base to determine a classification. This mathematical approach to classification, using vectors rather than image comparison, results in fast performance that imposes virtually no restrictions on system throughput.

The knowledge base starts with a set of standard defect classifications that fit many of the defect types typically encountered in lithography processes. These classes, in turn, are based on a standard set of local defect descriptors, such as size and edge sharpness. Additional descriptors provide such information as angle and distribution within a global context. Defects that do not fit any of the predefined classes are automatically categorized as unclassified and can undergo further review if necessary.

Establishing a new category is a two-step process. The first and most critical one involves expert human input to examine unclassified defects and determine whether a subset follows a consistent pattern that can be correlated to a functional defect mechanism. Once that correlation has been established, defining the new defect class in the knowledge base is straightforward. Given a few representative examples, the system can extract descriptor values automatically to define the class vector. The system can also resolve class overlaps by assigning appropriate weights to high-level descriptors within the class definition.

A key advantage of the knowledge-base system is that defect types can be classified according to existing fab rules. Anyone who has ever worked in the IC industry can attest to the fact that fabs or companies use a rich vernacular that is specific to them. At 1st Silicon, for example, the defect inspection system was trained quickly to identify the defect in Figure 3 as a “rat bite.” Once it had been trained, the system was able to identify similar defects as rat bites. This procedure provides correct information for statistical process control, enabling engineers to track unique defects consistently throughout the fab.

Figure 3: Image of a rat-bite defect, which was successfully incorporated into the knowledge-based classification scheme using only a few representative examples.

Fab Implementation of the Inspection System

A state-of-the-art 200-mm wafer foundry, the 1st Silicon fab in which the WaferView system was installed can produce 45,000 wafers per month at geometries from 0.25 to 0.13 µm. After considering the merits of adopting automated defect inspection, the fab acquired two inspection tools and a YieldView server to evaluate the system’s ability to improve yields in the lithography area.

The automated defect inspection system has a maximum throughput of more than 120 wafers per hour and can classify defects with better than 90% accuracy. The system’s server is a recipe and data management system that performs a variety of tasks: It creates off-line recipes, updates recipes automatically so that they can be used on multiple tools across the fab, defines alarm rules and sends appropriate alarms to the fab host, and retrieves, analyzes, and charts the large amounts of inspection data that are obtained from the inspection tools.

A joint evaluation project between the fab and the vendor consisted of three phases:

1. It developed the inspection recipes, alarm rules, and classification criteria to detect and classify the defect types of critical concern to the chipmaker.

2. It analyzed the data obtained in the first step to determine the critical sources of defects, thereby reducing rework.

3. It quantified the system’s contribution to yield enhancement and calculated the expected return on investment from acquiring the system.

Phase 1—Recipe Development. To maximize the initial benefits of installing the inspection system, the fab concentrated on one device and identified five critical layers for inspection from the front end, middle, and back end of the production process. They specified alarm rules and directed the server to send the process engineers an e-mail notification of every alarm incident. The engineers responded with appropriate corrective action. A plot of the alarms per project week is shown in Figure 4.

Figure 4: Number of failures per work week. Initially, the number of alarms was large because the recipes were immature and previously undetected process problems had not yet been discovered and corrected.

Initially, the number of alarms was high for two reasons: First, immature recipes, particularly related to color defects, generated a relatively large number of alarms that, upon expert inspection, were determined not to affect yields. As the recipes were optimized, the number of nuisance failures dropped rapidly. By week 4, the nuisance defects had been eliminated and the inspection system was reporting legitimate failures. Second, process problems that had not been detected or classified in the past were now detected and brought to the attention of the process engineers. As they worked to correct these defect modes, the number of alarms decreased.

Phase 2—Process Improvement. A defect Pareto chart for the first nine months after installation of the inspection system is shown in Figure 5. The chart tracks six defect types that were of particular interest, since they had been shown to contribute significantly to yield loss: color variation, particles, partial exposure, coating defects, scratches, and defocus.

Figure 5: Implementation of the automated inspection system substantially reduced the total number of defects in the lithography process at 1st Silicon.

Before the project started in March, the rate observed for the tracked defect types was comparatively high. Data from January and February were collected by the system using recipes that had not been optimized. At the beginning of the project, the defect rate jumped, at least partially because of an increase in reported color variation defects, many of which were not yield robbing. Increases in defocus and coating defects, on the other hand, resulted from the improved detection and classification achieved by using the inspection system.

By May, the recipes had been optimized and the reported defects had reached a lower level than before the project started. Significantly, the defects continued to decrease after the recipes were turned over to production in June because the process engineers were notified almost instantaneously about excursions, enabling them to diagnose and correct defect sources quickly.

For example, defocus errors are generally the result of particles on the wafer chuck. When a wafer is placed on the chuck, the area of the wafer above the particle becomes slightly elevated. In the expose step, the elevated area is out of focus. To prevent defocus, the inspection system was programmed to send an alarm to a process engineer any time a defocus defect occurred more than once in the same location. These alarms allowed the engineer to halt the process and remove the particle before further wafers were processed. As the data in Figure 5 show, this method reduced the number of defocus errors to almost nothing in September and October.

Phase 3—Cost Savings and Return on Investment. For the 10 months shown in Figure 5, the yield directly recovered from this joint project was significant. Based on reasonable assumptions about ongoing rework and recovery rates, the fab anticipates that its purchase of the two inspection tools and the associated server will achieve substantial annual cost savings. Most importantly, these direct cost savings—the actual recovered yield from reworked wafers—do not reflect the fact that the total number of defects was reduced to nearly one-fifth of their original number. Real savings will accrue as automated inspection is implemented throughout the foundry, resulting in the improved ability to identify and correct the sources of yield-robbing defects before they diminish yields.

Conclusion

The successful implementation of an automated defect inspection system to monitor the performance of the photo-lithography process at 1st Silicon has enabled the foundry’s process engineers to identify and eliminate the root causes of many troublesome defects. The fab has realized significant direct cost savings by being able to rework lithography defects. Even greater gains are anticipated from ongoing efforts to reduce and eliminate the sources of defects. Quicker process ramps, faster recovery from yield excursions, and higher ongoing yields at high volume will allow the fab to better service its customers while improving its own profitability.


Janet Goh Pau Ying is a senior process engineer at 1st Silicon in Kuching, Sarawak, Malaysia. Active in the semiconductor industry for four years, she received an honors degree in chemical engineering from the University of Adelaide in Australia. (Goh can be reached at +60 82 354888 or pygoh@1si.com.)

Shuba Chandar is regional applications support manager for Rudolph Technologies. Stationed in Singapore, he has 10 years of experience in the semiconductor industry, primarily in the areas of yields and in-line defectivity. He received a bachelor’s degree in chemical engineering from the University of Technology Malaysia in Skudai, Johor, and an MS in semiconductor physics from Multnomah College in Oregon. (Chandar can be reached at +6012 4759110 or schandar@rudolphtech.com.)

Tan Chang Ou is a senior customer engineer at Rudolph Technologies. With six years of experience in the semiconductor industry, he supports the yield enhancement methology and lithography group at 1st Silicon in Kuching, Sarawak, Malaysia. He received an honors degree in electrical and electronic engineering from the University of Hertfordshire in Hatfield, Herts, UK. (Tan can be reached at +60 13 8089555 or changou.tan@rudolphtech.com.)


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