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Wet Surface Technologies

Comparing single-wafer and batch polymer cleans using inorganic chemicals in BEOL applications

Terri Couteau, Gary Dawson, and John Halladay, Spansion; and Leo Archer, SEZ

As the semiconductor industry continues to progress, it is developing high-performance devices at the lowest cost of ownership possible.1 During the development phase of a novel device generation, increasing emphasis is placed on developing processes that focus on the manufacturability of particular products.2 To accommodate both the technical and cost requirements associated with high-volume manufacturing, the industry is increasingly relying on single-wafer processing, including in the area of wet cleans.3

Compared with traditional batch-type manufacturing, single-wafer wet cleaning offers better process control, a lower cost of consumables, and faster cycle times. The migration to single-wafer processing, which has been particularly strong in back-end-of-line (BEOL) processing, has resulted in both yield and cost improvements at many fabs, including at Spansion’s Fab 25 in Austin, TX.

Previously, the effects of implementing an inorganic BEOL postetch residue clean using a single-wafer tool were reported.4 At that time, the emphasis was on replacing large batch (wet-bench) systems using organic solvent–based chemistries with a single-wafer process using a dilute inorganic material. That low-price alternative resulted in a significant reduction in the process cost of ownership coupled with a marked improvement in wafer characteristics and increased device yields.5 It has recently been observed that the single-wafer inorganic BEOL postetch residue clean is also successful in both BEOL and FEOL DRAM applications.6

In the study presented in this article, the single-wafer inorganic BEOL postetch residue clean process was first implemented on select metal and contact layers. Eventually, all layers were transferred to the new process except for contact 1, which Spansion Fab 25 continued to perform in a batch spray tool using a chemistry that combined sulfuric acid and hydrogen peroxide (SPM) with an ammonia hydroxide–hydrogen peroxide–water mixture (APM). To complete the transfer of all BEOL cleans to the single-wafer process and clean contact 1 layers, evaluations were begun on the effectiveness of using DSP+ from Kanto (Portland, OR), a dilute sulfuric peroxide mixture. The study compared the effectiveness of a batch and a single-wafer process to remove postetch residue (polymer) on flash device wafers. To gather yield data, detailed wafer metrology and electrical characterization steps were performed.

Experimental Procedure

The contact 1 integration scheme differed from all other contact levels in that the contact was formed on CoSi2 instead of tungsten/titanium nitride. Two phases of boron and phosphorus-doped tetraethylorthosilicate (TEOS)–deposited oxide were used as interlayer dielectrics. The two oxide types were deposited at different rates. After mask deposition, exposure, dry etch, and resist removal, the residues were cleaned using a wet process step.

After an etch step was performed, wafers were split into four lots and then cleaned using either the process of record (POR) SPM/APM chemistry or one of three different DSP+ processes. Table I outlines the process conditions that were used.

Table I: Wet experimental conditions.

One set of wafers was processed using the POR on a spray tool from FSI (Chaska, MN). The remaining split lots were processed using DSP+ on a single-wafer spin processor 4200 from SEZ (Villach, Austria). The steps used in the SEZ clean were iterative: The chemical dispense sequence was repeated for a specified number of times, and each sequence was followed by a very short (<5 second) DI-water rinse. It has been shown previously that this approach results in the highest cleaning efficiency.5 Transmission electron microscopy (TEM) was used to determine the effect of the clean on the critical dimension (CD) of the contact structures. It was also used to show whether the cleaning process resulted in any apparent damage to the dielectric or the CoSi2 layer and whether bowing increased in the cavity walls. Contact resistance variations were also measured to indicate whether the wet clean had a deleterious effect on the electrical characteristics of the device.

Results and Discussion

Physical Characterization. Table II compares normalized CD measurements for the contact 1 structure after it was processed using one of the four cleaning methods. The table compares mask CD at the bottom of the contact area before and after cleaning—in other words, the CD of the original photoresist mask area used to form the contact hole and the final CD (FICD). The table also shows the CD bias.

Table II: Comparison between preclean and postclean mask CD and data for postclean CD bias. (The data are normalized.)

In general, running DSP+ processes on a single-wafer tool resulted in an FICD that was at least 5% less than that resulting from the use of the POR. (It is important to note that the standard deviations of the SEZ splits were slightly higher than that of the POR.) The result of the decreased FICD for the three single-wafer processes was lower CD bias on the order of 8 nm. The reduced CD bias was a consequence of the decreased oxide loss during single-wafer processing that resulted from a low oxide etch rate.

Figures 1 and 2 show representative TEM images of the contact 1 structure after processing in the batch tool using the POR versus in the single-wafer tool using DSP+. Halfway up the middle of the structure, measurements were taken along perpendicular (x and y) axes to determine the amount of contact bowing that resulted from the two cleaning approaches. The x-axis contact bow (Figure 1) was 15% less after the single-wafer 4x process than after the POR, while the y-axis bow (Figure 2) was 9% less. The remaining profile degradation was primarily associated with the dry etch step followed by the barrier metal deposition presputter process.

Meanwhile, the single-wafer process did not result in etch damage to either the CoSi2 layer or the dielectric film. Based on the CD-measurement and TEM analyses, it is reasonable to say that the use of a single-wafer wet clean process results in lower CD values and greater contact-hole uniformity than the POR.

Figure 1: TEM x-axis images of the contact 1 structure after (a) the POR/batch-tool clean and (b) the DSP+ 4x/single-wafer clean. The artifacts seen in the center of the images resulted from the dry etch step followed by the barrier metal deposition presputter process.
Figure 2: TEM y-axis images of the contact 1 structure after (a) the POR/batch-tool clean and (b) the DSP+ 4x/single-wafer clean.

The single-wafer process resulted in lower defectivity levels, as highlighted in Table III. The defect density stemming from the single-wafer 4x process was 25% less than that stemming from the POR. Defect categorization showed that the defects were either unclassified or embedded particles. As shown in Table III, the single-wafer process also resulted in 36% fewer defective die than the POR. These observations are consistent with the greater cleanliness and uniformity of the single-wafer process over the batch process.

Table III: Postclean defectivity levels and the number of defective die resulting from the four cleaning processes. (The data are normalized.)

Electrical Characterization. Improvements in the physical characteristics of the contact structure should lead to a corresponding improvement in the electrical device performance. A summary of electrical characteristics is shown in Table IV.

Table IV: Electrical characterization comparison for devices cleaned using the four processes. (The data are normalized.)

Despite the significantly smaller FICDs in the devices cleaned in the single-wafer tool, core contact resistance did not differ greatly between those devices and devices cleaned using the POR, although all three single-wafer cleans resulted in values that were higher than that for the POR clean. While N+, P+, and poly2 contact resistances were also higher for the wafers cleaned using the single-wafer process, the difference between them and the POR-cleaned wafers was not significant. Leakage current appeared to be lower in the single-wafer 2x and 3x splits than in the POR split, while it was nearly equivalent in the 4x split. In all cases, the measurement standard deviation was similar. Other than a small shift in periphery contact resistances, there were generally no other significant split dependencies in all the remaining wafer electrical tests performed. When a split dependency was observed, it was shown to result from wafer-to-wafer variations. The single-wafer clean appeared to provide contact resistance that was relatively equivalent to that of the batch process. The overall performance margin of the devices cleaned in the single-wafer process was expected to increase because of the increased overlay margin resulting from their smaller CDs.

Yield Data. The integration of the device wafers was completed, and the wafers were sent to sort at the end of the line. Typically, such devices undergo several rounds of testing. At sort 0, the die undergo stress testing and UV erase. At this stage, all wafer electrical testing is performed. At sort 1, the die are read and programmed, and then the devices are allowed to age. After the appropriate aging time has elapsed, the die are reread and erased at sort 2. Critical sort data are presented in Table V.

Table V: Yield increase or decrease for devices cleaned using the four processes.

Sort tests categorize die into several bins. In the sort 1 tests, the 4x prime die (die that did not require repair) experienced a large yield improvement of more than 5.5% (row 1). The corresponding number of die that had to be repaired decreased by more than 4% (row 2). The total yield improvement, calculated by adding rows 1 and 2, experienced a noticeable improvement of more than 1.2% for the single-wafer 4x wafers (row 3). Clearly, there was some split dependence that cannot be easily explained. There was also an increase of 3.67% in the number of die that passed and did not need repair (row 4). In the sort 2 tests, the prime die experienced a yield increase of 2.75% (row 5), while repaired-die yield decreased by 0.83% (row 6). The net effect was higher die yield of almost 2% (row 7). Furthermore, because more die tested as prime, die that previously would have failed were now available for recovery.

Conclusion

This article has described a fab test that compared batch and single-wafer approaches for performing postetch residue removal on contact 1 structures using inorganic chemistries. The tests concluded that the single-wafer clean process results in a more uniform contact feature with a tighter CD than the batch process. It also reduces defect levels significantly—a general characteristic of single-wafer cleans. Ultimately, the single-wafer process also improves device yields.

Acknowledgments

This article is an edited version of a paper that will be presented at the IEEE/SEMI Advanced Semiconductor Manufacturing Conference, to be held May 22–24, 2006, in Boston. The authors wish to thank the management of Spansion Fab 25 for their initial and continuing support for this project. In addition, special thanks go to Sal Buitron of SEZ America for his work on the process setup and the experimental execution.

References

1. ES Meieran, “21st Century Semiconductor Manufacturing Capabilities,” Intel Technical Journal 2, no. 4 (1998).

2. RA Gasser Jr., “Yield Learning and Volume Manufacturing of High Performance Logic Technologies on 200 mm and 300 mm Wafers,” IEDM Technical Digest 28, no. 1 (2001): 1–4.

3. A Hand, “Wafer Cleaning Confronts Increasing Demands,” Semiconductor International 24, no. 9 (2001): 62–66.

4. L Archer, S-A Henry, and D Nachreiner, “Removing Postash Polymer Residue from BEOL Structures Using Inorganic Chemicals,” MICRO 19, no. 6 (2001): 95–103.

5. L Archer and T Couteau, “Real Fab Comparisons Reveal Advantage to Inorganic-Based Polymer Removal,” Solid State Technology 45, no. 12 (2002): 43–46.

6. J-K Song et al., “Single-Wafer Polymer Removal on DRAM Structures Using Inorganic Chemicals,” Solid State Technology 48, no. 5 (2005): 36–40.


Terri Couteau is the lead engineer for lithography development and production at Spansion’s Fab 25 in Austin, TX. A senior member of the technical staff at Fab 25, she received a BS in physics from Sam Houston State University in Huntsville, TX. (Couteau can be reached at 512/602-0473 or terri.couteau@spansion.com.)

Gary Dawson is the photolithography module manager at Spansion Fab 25. He received a BS in chemical engineering from the University of Cincinnati and an MBA from St. Edwards University in Austin, TX. (Dawson can be reached at 512/602-0761 or gary.dawson@spansion.com.)

John Halladay, PhD, is the tool owner and process engineer for postetch plasma strip and BEOL wet cleans at Spansion Fab 25. He received BS and PhD degrees in microbiology from the University of Massachusetts and an MBA from the University of Texas in Austin. (Halladay can be reached at 512/602-2930 or john.halladay@spansion.com.)

Leo Archer, PhD, is VP of emerging technologies at SEZ in Phoenix. He received BS and PhD degrees in chemistry from the University of New Mexico in Albuquerque. (Archer can be reached at 602/453-5023 or larcher@us.sez.com.)


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