Copper/low-k dielectric interconnect has legs, but for how long?
The replacement of aluminum with copper and the advent of low-k dielectric insulators in logic back-end-of-line interconnect schemes has been one of the most successful materials integration change-overs in chipmaking history. Although it appears the damascene tandem will continue to push down the scaling roadmap for awhile, alternative interconnect options will be needed in the not-too-distant future. This issue’s Hot Button participants weigh in on the background, current and near-term outlook, and longer-term challenges of BEOL processing.
STEPHEN LUCE (distinguished engineer, IBM Microelectronics): Chip performance continues to improve with each technology generation. This steady progress is driven by predictable improvements in transistors and ongoing enhancements in chip architecture. Delay from chip interconnects was not a serious limiter to ever-increasing chip speeds for the first three decades of IC manufacturing, so the interconnect material set of aluminum conductors and silicon dioxide insulators remained unchanged.
But in the mid-to-late 1990s, chip speeds had increased to a point where interconnect delay became a critical factor affecting overall performance. Starting with 180-nm technology, most companies building high-performance devices began to recognize the increasing impact of interconnect delay and started to make improvements in wire resistance and capacitance. Fluorine was commonly added to the silicon dioxide insulators to improve the dielectric constant (k) from 4.1 to around 3.6, which provided a reduction in interconnect capacitance.
Copper replaced aluminum at 130 nm (even earlier at IBM and a few other companies), resulting in lowered metal resistance. The dielectric constant improved again at 90 nm, with the implementation of carbon-doped oxide (CDO) with a k value of around 3.0 as the most common insulator material. When several companies launch 65-nm production this year, it appears that second-generation CDO insulators will be the most widespread choice, accompanied by incremental enhancements in the dielectric constant.
Transistor improvement is projected to continue at the same pace for the next several generations, so the need for ongoing improvement in interconnect performance continues. The International Technology Roadmap for Semiconductors (ITRS) predicts that by 2014, the dielectric constant will improve to a very aggressive value of <2.0. This goal is driving some challenging integration and materials work by teams around the world. There is a direct relationship between dielectric constant and the mechanical behavior of the insulator material. The addition of porosity and other “tricks” that improve dielectric constant weaken the materials and introduce integration problems. Materials engineering for these insulator films is a key focus area for the interconnect community.
Excellent progress has been made in improving insulator materials with optimized compositions and enhanced cures. But plenty of work remains. Chemical vapor deposition of CDO materials is likely to be the common choice for 65 nm, but several options are under evaluation for 45 nm and below. Work continues with spin-on materials, including all-spin-on options and hybrid combinations with CVD films. There are also significant efforts by several teams to develop air gap, the ultimate low-dielectric-constant insulator, which fills much of the space between the wires with air. Although implementation is still a few generations away, good progress is being made.
It is unlikely that there will be a transition away from copper, but shrinking wire dimensions are creating significant challenges. Since liners typically have much higher resistance than copper, providing a liner that has complete coverage without replacing too much copper is becoming increasing difficult with each generation. Physical vapor deposition (PVD) of tantalum-based materials—the typical liner process for 130, 90, and likely 65 nm—has been driven by constant improvement in equipment and processes. PVD technology is in the running for sub-65 nm, but there are also intensive efforts under way to investigate alternatives, including several CVD-based films and self-forming barriers that have the potential for thinner films.
Although copper wires with reduced-dielectric-constant insulators will continue to be the mainstay of interconnect schemes for awhile, the relentless drive for better chip performance will ultimately foster a transition to new interconnect concepts.
HAROLD HOSACK (director, interconnect and packaging sciences, Semiconductor Research Corp.): The need for interconnect concepts beyond the conventional metal/dielectric system has been brought on by the continued increase in the frequency and power of ICs, and the continued push to smaller geometries to satisfy the needs of Moore’s Law. The dramatic reversal that has occurred in high-performance ICs—from performance limited by transistor delay to performance limited by interconnect delay— clearly shows the inadequacy of continuing with the approach of scaling the conventional metal/dielectric system to meet future interconnect requirements.
Multiple alternative options have been devised to replace or modify the metal/dielectric system and to solve the delay/power problem. Some of the most promising options under consideration are, in order of increasing complexity of integration, as follows:
• Using different signaling methods, such as raised cosine waveforms and resonant clocks.
• Extending the interconnect solution into other parts of the IC structure, such as using interconnect-centric design, package-intermediated interconnects, or chip-package codesign.
• Exploiting the third dimension in 3-D ICs.
• Applying different physics, such as optical interconnects and RF/microwave interconnects.
• Resolving the interconnect problem by using radical solutions, such as nanowires/nanotubes or molecular interconnects.
Although some of the new approaches are potentially quite versatile, it appears that no single solution will be universally applicable to all interconnect levels in future ICs. This is in stark contrast to the situation that has prevailed with aluminum/silicon dioxide and copper/low-k dielectric interconnect schemes. For the foreseeable future, the incumbent Cu/low-k metallization approach will continue as an important part of the total interconnect and will be supplemented by one or more of the alternatives noted above as a total interconnect solution for specific applications. This presents a major challenge to the IC technology community, because it requires not only developing novel alternative interconnects, but also continuing to push the incumbent metal/dielectric methods to their ultimate limits.
Progress on alternative interconnect approaches, as well as on the continued evolution of the metal/dielectric system, can be followed through publications and presentations at specialized technical conferences such as the IEEE International Interconnect Technology Conference (IITC) and the IEEE International Electron Devices Meeting (IEDM). The maturing of specific choices among the many entries in the race for novel interconnects will be evidenced by the appearance of technology roadmaps in the ITRS and other specialized documents and presentations.
(This year’s IITC takes place June 5–7 at the Hyatt Regency San Francisco Hotel in Burlingame, CA. For more information, check www.his.com/iitc.)
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© 2007 Tom Cheyney
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