RequestLink
MICRO
Advertiser and
Product
Information

Buyer's Guide
Buyers Guide

tom
Chip Shots blog

Greatest Hits of 2005
Greatest Hits of 2005

Featured Series
Featured Series


Web Sightings

Media Kit

Comments? Suggestions? Send us your feedback.

 

MicroMagazine.com

Transistorama

Developing a systematic approach to metal gates and high-k dielectrics in future-generation CMOS

Prashant Majhi, Huang-Chun Wen, Husam Alshareef, H. Rusty Harris, Hongfa Luan, Kisik Choi, C. S. Park, Seung-Chul Song, Byoung Hun Lee, and Raj Jammy, Sematech

Nearly a decade has passed since
the semiconductor industry began a serious evaluation of high-k materials as potential gate dielectrics for future-generation CMOS devices. The goal of the evaluation was to overcome the exponentially increasing gate leakage that occurs with the scaling of conventional SiON dielectrics.1 Excellent progress has been made in recent years in demonstrating the viability of high-performance devices incorporating hafnium-based high-k dielectrics.2-4 However, it has become clear that high-k dielectrics are incompatible with polysilicon gate electrodes in devices with low threshold voltage (Vt), which is attributed to the Fermi-level pinning phenomenon.5 Hence, research on the use of metal gate electrodes to replace conventional polysilicon has gained momentum. Additionally, by using metal gates, it is possible to achieve lower equivalent oxide thickness (EOT) in inversion (i.e., without poly depletion), lower gate resistance, and the elimination of boron penetration from the doped polysilicon into the gate dielectric and transistor channel.

An early paper from 1997 discussed the need for metal gates in future-generation scaled CMOS devices.6 Nevertheless, consensus is still limited on the candidate material systems for metal gate applications and how to integrate them at the technology nodes where high-k dielectrics will first be implemented. The primary reasons for this lack of consensus are an inaccurate methodology for extracting the effective work function (EWF) of metal gates, especially in the presence of fixed charges in the high-k material, and a limited understanding of the factors that control the EWF of metal gates. Additionally, because the CMOS flow and the short-loop flow needed to extract the EWF of metal gates involve dissimilar thermal budgets and gate-stack structures, manufacturing devices with appropriate Vt based on short-loop work function values has been difficult. To address this critical problem, metal gate researchers at Sematech (Austin, TX) followed a structured problem-solving methodology that involves:

1. Building consensus on metal gate specifications and developing a methodology to extract the EWF of metal gates accurately.

2. Using this methodology to extract EWF and understanding the intrinsic material properties and extrinsic process-induced properties that control the EWF of metal gates.

3. Understanding how to identify materials and integration pathways to realize appropriate metal EWF and, therefore, device Vt.

4. Studying scaled transistor devices with potential electrodes to evaluate the influence of metal gate materials and their influence on other device properties, including reliability issues.

5. Addressing module-level issues that must be resolved to integrate dual metals in CMOS devices.

The following article focuses on Sematech’s contributions and achievements in the area of metal gate/high-k dielectric research.

Metal Gate Specifications and Accurate Metal Gate EWF Extraction

Table I shows EWF specifications for metal gates in two different applications: CMOS on bulk silicon (band-edge EWF) and CMOS on fully depleted silicon on insulator (SOI) and FINFETs (near-midgap-tunable EWF). The process conditions for these applications are:

• The gate stack is subjected to a source/drain dopant activation anneal of 1000°C for 5 seconds.

• Conformance to EOT (gate-leakage specifications for high-k/metal gate stacks for high-performance and low-standby-power applications).

• Vt = ±0.1 V of control SiO2 with the same EOT.

• Vt stability = ±10 mV of unstressed film.

• Mobility ≤85% of SiO2.

• Density of interface traps ≤5 × 1010/cm2 eV.

• High-frequency (100-kHz) capacitance-voltage hysteresis ≤10 mV.

• Reliability comparable to poly/SiO2.

• Defect density ≤0.14 defects/cm2.

• Thickness uniformity (3 σ) ≤4%.

Table I: Gate electrode specifications.

The main property of interest is the EWF value, since it determines the Vt of the transistor. Ideally, the work functions of metals are measured by Kelvin probe, field emission, thermionic emission, retarding field emission, and ultraviolet photoemission spectroscopy techniques. However, for CMOS applications, the parameter of interest is the effective work function, which ultimately determines the flat-band voltage (Vfb) and hence the Vt of the transistor.

Since metals will be introduced with high-k dielectrics, there has been a significant effort to extract the EWF of metals on high-k dielectrics using a capacitance-based methodology. However, because high-k dielectrics are typically prone to high levels of bulk charge, the quality of the interface between the high-k material and the silicon is dependent on high-k thickness, making it very difficult to accurately determine the EWF of metals on high-k simply by studying the dependence of Vfb on high-k thickness. In fact, in some cases (e.g., tantalum nitride), the disparity in reported EWF values for the same material from different research groups is even larger than the band gap of silicon.7

To address this problem and develop a standardized technique to measure EWF, an improved procedure was developed by Sematech researchers.8 In this method, an entire range of oxide thicknesses is formed on a wafer by growing a relatively thick oxide and selectively etching back regions using a benign wet etchant. Evaluating the metal gate work function on high-k material can be done by depositing high-k dielectric material with a fixed thickness on this terraced oxide. A schematic diagram of a simplified three-charge model and an equation used to correlate Vfb to measured EOT and the barrier height difference is shown in Figure 1. It has been demonstrated that this terraced-oxide (capacitance-voltage) technique exhibits excellent linear Vfb-EOT fits and minimizes effects from variations in the fixed charge at the silicon oxide/silicon interface.

Figure 1: (a) An enhanced image schematic of a terraced-oxide wafer with corresponding oxide thickness bands, and (b) Vfb-EOT plot for effective work function extraction of TiN electrode. (The work function = 4.66 eV.)

The current-voltage (I-V) technique, a complementary method for extracting the EWF, uses leakage-current data to measure the height of the metal/high-k barrier. Shown in the schematic drawing in Figure 2a, this technique accurately determines the change in leakage mechanism from direct tunneling to Fowler-Nordheim tunneling.9 However, reasonable accuracy has also been achieved using the C-V technique on a set of samples with varying EWF. As demonstrated in the chart shown in Figure 2b, the values extracted from the I-V technique compared with those from the C-V technique showed a strong correlation, validating the viability of extracting EWF values using the terraced-oxide technique.

Figure 2: (a) A band diagram showing MOS structure at onset of leakage mechanism change (applied voltage at peak of derivative leakage current equals the metal/SiO2 barrier height), and (b) a chart comparing EWF extracted using C-V versus I-V techniques.

Controlling EWF and Screening Gate Stack Materials

EWF was evaluated on short-loop terraced-oxide capacitors whose gate stacks were identical to transistor devices in two respects: They had the same structure (thin metal capped with polysilicon), and they underwent the same high-thermal-budget processing (including source-drain-dopant activation anneals). Based on a comprehensive analysis of several stacks, it became clear that the EWF is influenced by various elements in the gate stack, shown schematically in Figure 3. The elements are:

Polysilicon. The polysilicon causes a stress reaction with the electrode if a barrier layer is not present.

Barrier/Cap Layer. The barrier/cap layer causes a stress reaction with the metal electrode, metal diffusion through the electrode grain boundary, and pile-up at the top interface layer (TIL). An overlay effect occurs if the electrode is very thin.

Metal Electrode. The metal electrode is the main contributor to EWF, crystallinity, grain orientation, and the thickness effect. An overlay effect occurs if the TIL is intentionally very thin.

Top Interface Layer. The TIL controls EWF if it is a conductive film.

Dielectric. The dielectric reacts with metal to form the TIL. Fermi-level pinning and fixed charges shift the Vfb.

Figure 3: Schematic diagram of elements in the gate stack that contribute to EWF change.

Of all these effects, the one that has the most significant effect on EWS is the structure of the TIL (high-k metal). With that understanding, Sematech researchers followed two approaches to develop promising metal-gate solutions: They identified and optimized material systems that exhibit appropriate EWF values, and they engineered the EWF by introducing interface layers between the metal gate and the high-k. Figure 4a shows a schematic diagram of a device with the metal layer directly on top of the Hf-based dielectric, while Figure 4b presents a diagram of a device with an interfacial layer between the metal and the high-k material.

Figure 4: Two integration approaches for achieving desired metal gate work function: (a) metal directly on Hf-based dielectric, and (b) interfacial layer at metal/high-k interface.

A wide range of EWF values for a wide range of material systems (even after high-temperature anneals) were realized using both of these approaches, as shown in Figure 5. Interestingly, there appeared to be little evidence of Fermi-level pinning for several of the materials that were tested. Several hypotheses—including Fermi-level pinning, the formation of metal-induced gap states as a result of the penetration of wave function from the metal into the dielectric, and the presence of dipoles at the metal/high-k interface—have been proposed to explain the observed shift in the metal gate EWF from its bulk work function value and its dependence on the dielectric.10

Figure 5: EWF extracted using the terraced-oxide technique. The various metal gate materials with identified band-edge n- and p- metals are on different high-k dielectrics. The circled areas represent EWF targets. (Data were gathered after a 1000°C anneal.)

Clearly, the data in Figure 5 demonstrate the feasibility of using metals with the appropriate EWF on high-k dielectrics. Consequently, the next logical step was to demonstrate the Vt correlating to the EWF that was extracted from the terraced-oxide capacitors.

Vt-EWF Correlation and Device Attributes of Band-Edge Metals on High-k Dielectrics

Several transistors with a range of metal gates exhibiting a wide range of EWF values were processed. From the Vt of long channels, metal gate EWF was back-calculated and compared with the extracted EWF from the same materials processed on terraced oxides, as shown in Figure 6. There seemed to be a very good correlation between Vt and EWF, again validating the accuracy of extracting the EWF using the terraced-oxide technique. For the few systems that did not correlate well, there was strong evidence of gate-stack disintegration (i.e., phase segregation in ternary metal systems and metal diffusion across gate dielectric stacks for scaled transistors).11

Figure 6: Comparison of terraced-oxide work function and transistor Vt-estimated work function for the same metal/high-k stack.

A study of the various metal gate systems on high-k dielectric indicated that not only the metal gate materials themselves, but also their processing conditions, influenced the device properties of the gate stack.12 Despite these extrinsic (process-dependent) challenges, Sematech researchers were able to develop stacks using band-edge metals with appropriate EWF that are suitable for bulk CMOS applications, as demonstrated in Figure 7.

Figure 7: Transistor characteristics of different metals on high-k dielectrics.

Although it is not altogether clear how these metals influence properties such as mobility, the data show that promising advances have been made in developing well-performing unichannel transistor stacks using band-edge metal on high-k dielectrics. The next logical step was to address the module issues in order to integrate these metals in CMOS devices.

Integrating Dual Metals in CMOS Devices

In conventional CMOS stacks, the different EWF requirements of NMOSFET and PMOSFET are easily achieved by doping the polysilicon gate during the self-aligned source/drain implantation process. However, to fabricate metal gates that meet the requirements of NMOSFET and PMOSFET Vts, it is necessary to benignly integrate two different metals on the same dielectric layer. Several process routes have been proposed to achieve this integration.13

Sematech researchers have resolved several etch-related issues, enabling them to integrate two very dissimilar materials such as ruthenium and TaSiN on the same dielectric layer without compromising high-k quality, as illustrated in Figures 8 and 9. These two materials were selected to demonstrate the feasibility of the integration pathway and are not necessarily the leading candidates for band-edge dual-work-function metals. Hence the relatively high device Vt shown in Figure 9. Sematech researchers have also demonstrated that metals with an EWF that has been engineered using interface layer insertion, as described in Figure 4, can be integrated in CMOSFETs. The resulting low Vts for NMOSFETs and PMOSFETs demonstrates again the feasibility of fabricating fully integrated metal/high-k transistors to meet the specifications of future-generation CMOS devices.14

Figure 8: Cross-section scanning electron microscope images (top) and transmission electron microscope images (bottom) of (a) NMOS and (b) PMOS regions processed using a dual metal CMOS flow.
Figure 9: Transistor CVs for NMOS and PMOS regions processed using a dual metal CMOS flow.

Conclusion

Metal gate electrodes have become imperative to realize high-performance scaled devices incorporating high-k dielectrics in future-generation CMOS gate stacks. With a structured problem-solving approach, Sematech researchers have been able to address many of the major challenges facing the successful identification and integration of metal gate electrodes on hafnium-based high-k dielectrics. Although a comprehensive understanding is lacking on how metal gate materials and their processing influence device performance (including reliability), recent Sematech advances show promise in realizing high-performance CMOS devices utilizing high-k dielectrics and metal gates.

References

1. BH Lee et al., “Ultrathin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gate Dielectric Application” (paper presented at the IEEE International Electron Devices Meeting, December 5–8, 1999, Washington, DC).

2. R Chau et al., “High-k/Metal–Gate Stack and Its MOSFET Characteristics,” IEEE Electron Device Letters 25, no. 6 (2004): 408–410.

3. Z Zhang et al., “Co-Optimization of the Metal Gate/High-k Stack to Achieve High-Field Mobility >90% of SiO2 Universal Mobility with an EOT = ~1 nm,” IEEE Electron Device Letters 27, no. 3 (2006): 185–187.

4. MA Quevedo-Lopez et al., “High Performance Gate First HfSiON Dielectric Satisfying 45nm Node Requirements” (paper presented at the IEEE International Electron Device Meeting, December 5–7, 2005, Washington, DC).

5. CC Hobb et al., “Fermi-Level Pinning at the Polysilicon/Metal-Oxide Interface—Part II,” IEEE Transactions on Electron Devices 51, no. 6 (2004): 978–984.

6. JC Hu et al., “Feasibility of Using W/TiN as Metal Gate for Conventional 0.13 µm CMOS Technology and Beyond” (paper presented at the IEEE International Electron Devices Meeting, December 7–10, 1997, Washington, DC).

7. P Majhi et al., “Evaluation and Integration of Metal Gate Electrodes for Future Generation Dual Metal CMOS” (paper presented at the International Conference on Integrated Circuit Design and Technology, May 9–11, 2005, Austin, TX).

8. GA Brown et al., “An Improved Methodology for Gate Electrode Work Function Extraction in SiO2 and High-k Gate Stack Systems Using Terraced Oxide Structures” (paper presented at the IEEE Semiconductor Interface Specialists Conference, December 9–11, San Diego, CA).

9. S Zafar, E Cartier, and EP Gusev, “Measurement of Barrier Heights in High Permittivity Gate Dielectric Films,” Applied Physics Letters 80, no. 15 (2002): 2749–2751.

10. HN Alshareef et al., “Gate Electrode Development for Dual Metal-Gate CMOS Applications,” Future Fab International 19 (June 2005): 91–93.

11. HC Wen et al., “Systematic Investigation of Amorphous Transition-Metal-Silicon-Nitride Electrodes for Metal Gate CMOS Applications” (paper presented at the International Symposium on VLSI Technology, June 14–16, 2005, Kyoto, Japan).

12. P Majhi et al., “Influence of Metal Gate Materials and Processing on Planar CMOS Device Characteristics with High-k Gate Dielectrics” (paper presented at the European Solid-State Device Research Conference, September 20–24, 2004, Leuven, Belgium).

13. ZB Zhang et al., “Integration of Dual Metal Gate CMOS with TaSiN (NMOS) and Ru (PMOS) Gate Electrodes on HfO2 Gate Dielectric” (paper presented at the International Symposium on VLSI Technology, June 14–16, 2005, Kyoto, Japan).

14. SC Song and et al., “Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS” (paper to be presented at the International Symposium on VLSI Technology, April 24–26, 2006, Hsinchu, Taiwan).


Prashant Majhi, PhD, is an Intel assignee to Sematech (Austin, TX). He manages the planar CMOS scaling group and advanced gate electrodes project. He joined the process development group at Philips Semiconductor in The Netherlands in 2000 and was the project leader in module development for several CMOS and mixed-signal process technologies. Majhi has authored or coauthored more than 100 papers and holds several IC process-development patents. He received a bachelor of technology degree from the Indian Institute of Technology in Madras and a PhD in science and engineering of materials from Arizona State University in Tempe. (Majhi can be reached at 512/356-3151 or prashant.majhi@sematech.org.)

Huang-Chun Wen works on the electrical characterization and reliability measurements of metal-gate and high-k dielectric layers through an internship in the advanced metal electrode program at Sematech. She received BS and MS degrees in electrical engineering from National Chiao Tung University in Hsinchu, Taiwan, and is pursuing a PhD degree in electrical and computer engineering at the University of Texas in Austin. (Wen can be reached at 512/356-7166 or huang-chun.wen@sematech.org.)

Husam Alshareef, PhD, is a member of technical staff at Texas Instruments and is an assignee to Sematech. The author of more than 100 publications, he holds 30 patents. He received a PhD in materials science from North Carolina State University in Raleigh. (Alshareef can be reached at 512/356-3388 or husam.alshareef@sematech.org.)

H. Rusty Harris, PhD, works for Advanced Micro Devices (AMD) in the area of high-k/metal-gate process integration, germanium channel devices, and epitaxial process development as an assignee to Sematech. He initiated the design and construction of a $1.9 million semiconductor lab at the University of Missouri while teaching undergraduate classes as a visiting assistant professor. He received a BS in engineering physics and an MSEE from Texas Tech University in San Marcos. He also received a PhD in electrical engineering in the area of surface and interface analysis for silicon devices from Texas Tech University in Lubbock. (Harris can be reached at 512/356-7883 or rusty.harris@sematech.org.)

Hongfa Luan, PhD, joined the metal gate electrode group of the front-end processes division at Sematech in 2004 as a project engineer. An assignee from Infineon Technologies, he focuses on MOCVD to develop dual metal gate materials and processes and works in cooperation with tool suppliers to identify different precursors. He also works on PVD and ALD process development. He has spent five years working in the high-k area and has process experience in all semiconductor fields. Previously, he worked at Teravicta Technologies and Radiant Photonics. He received a PhD in engineering from Beijing University of Science and Technology. (Luan can be reached at 512/356-7436 or hongfa.luan@sematech.org.)

Kisik Choi, PhD, is a project engineer at Sematech. Previously he worked for the consortium as a postdoctoral researcher. Before that, he served as a manager at the Hyundai Electronics Semiconductor R&D center (now Hynix) in Inchon, South Korea. He holds 13 registered patents and has authored or coauthored dozens of articles in industry professional journals and conference proceedings. He received BS and MS degrees in materials science and engineering from Seoul National University in South Korea and received a PhD in electrical engineering from Texas Tech University in Lubbock. (Choi can be reached at 512/356-3035 or kisik.choi@sematech.org.)

C. S. Park, PhD, joined Sematech in 2005 to work on process development and integration projects in the area of metal/high-k gate stacks. He joined Hynix Semiconductor (formerly Hyundai Electronics) in 1993 and then became a clean staff engineer at Tower Semiconductor in 1999. He received a BS in ceramic engineering at Yonsei University in Seoul, South Korea, and a PhD in electrical engineering at National University in Singapore. (Park can be reached at 512/356-3619 or c.s.park@sematech.org.)

Seung-Chul Song, PhD, is a project manager in the front-end processes division at Sematech, where he focuses on planar and nonplanar CMOS integration and device research associated with dual metal gate and high-k dielectric stacks. Previously, he worked at Motorola in the semiconductor products sector and at Samsung Electronics. He participated in 0.15-, 0.13-, and 0.1-µm CMOS process integration and device research. The author or coauthor of more than 50 conference and journal papers, he received a BS from the University of Inchon in South Korea and an MS from the University of Texas in Austin in materials science and engineering. He also received a PhD in electrical and computer engineering from the University of Texas. (Song can be reached at 512/356-3544 or s.c.song@sematech.org.)

Byoung Hun Lee, PhD, is on assignment at Sematech as a manager of the advanced gate-stack program. He manages advanced dielectric, electrode, baseline, and electrical characterization projects. He worked at Samsung Semiconductor and has been with IBM since 2001. Lee has authored or coauthored more than 220 journal and conference papers in the areas of gate oxide reliability, SOI devices and processes, strained-silicon devices, and high-k and metal gate processes and devices. He received BS and MS degrees in physics from the Korea Advanced Institute of Science and Technology in Daejeon, South Korea, and a PhD in electrical and computer engineering from the University of Texas in Austin. (Lee can be reached at 512/356-3115 or byoung.hun.lee@sematech.org.)

Raj Jammy, PhD, is on assignment from IBM as director of the front-end processes division of Sematech. He joined IBM’s Semiconductor Research and Development Center in East Fishkill, NY, where he worked on the development of ultrathin dielectrics, advanced doping techniques, and other front-end technologies for deep-trench DRAMs. In 2001 he was appointed manager of the thermal processes and surface preparation group, with additional responsibilities in CMP, thin films, and metallization in the DRAM development organization. He moved to IBM’s T. J. Watson Research Center in Yorktown Heights, NY, in 2002 to manage high-k gate dielectric and metal-gate efforts. He received a PhD in electrical engineering from Northwestern University in Evanston, IL. (Jammy can be reached at 512/356-3098 or raj.jammy@sematech.org.)


MicroHome | Search | Current Issue | MicroArchives
Buyers Guide | Media Kit

Questions/comments about MICRO Magazine? E-mail us at cheynman@gmail.com.

© 2007 Tom Cheyney
All rights reserved.