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Critical Materials

Identifying and eliminating unique copper electroplating defects

Ted Cacouris, Chee Ping Lee, and Augustine Teo, Novellus Systems;
and Li Chaoyong and He Xin, Chartered Semiconductor

Copper electroplating in IC manufacturing applications has evolved significantly in recent years, particularly in its ability to fill high-aspect-ratio features and improve defectivity. While defect analysis tools were inadequate when the technology was in an early stage of development, advances have enabled engineers to identify and classify several different defect modes that are unique to electroplating. In this article, engineers from Novellus Systems (San Jose) and Chartered Semiconductor (Singapore) examine a defect mode that resulted in yield losses on device wafers and explain the methods they developed to eliminate it.

Electroplating Advances

Copper electroplating technology has developed rapidly as the requirements for dual-damascene interconnects have continued to change. While early electroplating techniques focused primarily on chemistries and processes to fill fine features without voiding, the technology has expanded to address several other concerns, including defectivity, optimization of the copper microstructure, and elimination of impurities that decrease yields and reduce device reliability.

Typically, engineers have addressed these issues by changing electrolyte additives and the plating process itself. However, chemistry and process changes can result in different degrees of film roughness. Until defect metrology tools were tuned to discriminate between inherent surface morphology and defects on electroplated copper films, certain defect modes were not well understood. Most defects were observed after chemical-mechanical planarization (CMP) was performed, but differentiating between plating- and CMP-induced defects posed a significant challenge. For example, defects that were generally categorized as missing copper could have resulted from corrosion, from scratches caused during CMP, or from incomplete filling of fine features after plating.

Many device manufacturers still rely heavily on post-CMP defect metrology as the primary method for determining the yield impact of defects in copper metallization processes. In contrast, Chartered Semiconductor performed postelectroplating defect analysis to differentiate among defect sources and develop process improvements. Systematic defect-reduction activity focused on separating CMP-induced defects from those created during plating. As a result of this analysis, missing-copper defects, whose counts per wafer and frequency varied depending on the plating tool in which the wafers were processed, appeared before CMP.

Defect Classification Background

Since the implementation of copper interconnects in 1998, refinements in defect metrology and elimination methods have continued to improve. A key development on the metrology front has been the ability to distinguish between background reflectance and actual in-film defects using optical instruments. Over time, Novellus has developed an extensive defect library with links to their sources, including plating chemistry, process conditions, and hardware. Examples from the library include:

• Particulate defects that are embedded in the plated film or reside at the surface after plating (Figure 1).

Figure 1: Example of a particle defect on top of (left) and embedded in (right) a plated copper film.

• Chemistry-driven protrusion defects that result from abnormal, accelerated grain growth (Figure 2).

Figure 2: Protrusion defect in a plated copper film.

• Pit defects caused by the absence or retardation of growth at particular points on the wafer (Figure 3).

Figure 3: Pit defect in a plated copper film.

Through equipment hardware design improvements and process optimizations, particulate defects can be minimized substantially. Hence, this type of defect is not discussed here.

Protrusion defects are more common with highly “accelerated” chemistries, where additive concentrations enable high growth rates. For example, chemistries with high copper concentrations commonly exhibit protrusion defects. Such defects can be minimized by optimizing processes and chemistries. By shifting the kinetics of the process to a mass-transfer-limited regime (higher plating currents and/or lower wafer rotation rates) and by adding suppressing agents such as levelers to the chemistry, protrusion defects can be reduced to extremely low levels. Although protrusion defects are not killer defects, they represent a nuisance during defect inspection, potentially masking yield-limiting defects.

Yield-limiting defects such as pits have been studied extensively. Consequently, their source components are well understood. Several subclassifications of pit defects, based on appearance and root cause, have been defined. Generally small in size, round pit defects (0.1 to 0.5 µm) form in areas where copper plating was inhibited because of incomplete wetting or the presence of an air bubble. This situation can arise from local microcontamination of the seed surface by airborne contaminants or contaminants embedded in the seed. The defects’ round shape reflects the imprint created by an air bubble. A related defect, known as a crater, has a similar origin as a pit defect but differs primarily in its size.

As illustrated in Figure 4, crater defects are usually several microns in size.

Figure 4: Crater defect.

The Formation of a Swirl Defect Pattern

Since most manufacturers anneal plated copper films immediately after plating to enable grain growth and low resistivity, in-film defect metrology is often performed after this step. At Chartered, defect metrology performed after electroplating anneal indicated that pit defect counts varied substantially from wafer to wafer and tool to tool. In an extreme case, a well-defined swirl signature on the wafer was evident, as shown in Figure 5.

Figure 5: Defect pattern showing swirl signature.

To immerse wafers in a plating bath without trapping bubbles beneath them, tools are designed to tilt the wafer with respect to the liquid surface during immersion or entry. The optimum tilt angle is constrained by the need to allow air to escape quickly from underneath the wafer and the need to immerse the entire wafer rapidly in order to minimize the time difference between the first point of immersion and the last. In addition, a bias is typically applied to the wafer during entry to prevent seed dissolution, while the wafer is rotated to achieve sufficient chemical agitation.

Pit defects in the shape of a swirl can be ascribed to the wetting pattern the wafers experience during initial immersion into the plating solution. This characteristic pattern can vary as a function of vertical immersion speed (z-speed), rotation rate (in revolutions per minute), and tilt angle. Simple modeling of the wafer entry conditions can recreate the pattern from a series of chords, representing partial immersion, as shown in Figure 6. In effect, a corkscrew pattern develops, revealing that the wafer rotation is relatively faster than the vertical entry speed, so that parts of the wafer are immersed and then momentarily removed from the solution before being immersed completely. This wetting/dewetting phenomenon leaves a mark on the wafer in the form of a series of pits.

Figure 6: Modeling of a swirl pattern as a series of chords representing the wetted area as the wafer enters the plating solution at an angle while it is spinning.

Changes in any of three parameters (angle, revolutions per minute, and z-speed) can modulate the shape of the wetting pattern. The frequency and incidence of this pattern is highly dependent on starting wafer-surface quality—that is, the copper seed surface. Varying degrees of surface oxidation resulting from air exposure, contamination from airborne agents, and variations in the barrier/seed process can influence the wetting pattern. Chemistry formulations also play a key role. For example, the surfactants added to some chemistries to improve wetting can affect the defect mode, even though the wetting pattern resulting from the entry of a wafer into the plating bath is consistent across wafers and lots.

Eliminating Electroplating Defects

Root-Cause Analysis. Armed with knowledge about defect formation, a systematic comparison was performed across the fleet of plating tools at Chartered to identify differences among them. At least one plating tool was identified as generating consistently lower defect counts than the other tools and was therefore used as a baseline. Inorganic and organic chemistry concentration variances across the tools were ruled out, because good matching had been achieved. In addition, plating-bath temperatures were matched, since chemistry temperature can affect defect frequency and magnitude. Key hardware settings, including z-speed, rotation rate, and tilt angle, were also matched.

The plating-tool comparison discovered that wafer immersion depth correlated with a higher incidence of defects. When a wafer is not immersed deeply enough in the plating solution, it can entrain air bubbles from the liquid surface during rotation, exaggerating the defect mode. In contrast, a sufficiently immersed wafer does not suffer from this type of defect generation.

Solving Defect Problems. Defect improvements were implemented in two stages. First, all tools were matched to the best-performing tool, whereby wafer immersion emerged as a statistically significant difference among them. Second, the root cause of the defect phenomenon was addressed by eliminating the swirl signature. To validate that these steps had a beneficial effect, a defect test vehicle for representing the worst-case results without relying on a large data sample was needed. Developed by Novellus, such a vehicle was used to characterize potential hardware and process solutions.

The first round of improvements—tool matching—primarily reduced the defectivity variance across all the tools. Although this exercise clearly uncovered some inconsistencies in the tool fleet, it did not affect mean defectivity significantly.

In contrast, it was found that changing how wafers entered the plating cell could eliminate the swirl entry pattern. By modeling the wafer entry conditions that produced the swirl pattern, fab investigators were able to modify the key parameters and eliminate the pattern. The optimum combination of wafer rotation rate, z–speed, and angle resulted in uniform wetting, as illustrated in Figure 7. After these modifications, the wetted area of the wafer swept across the substrate surface without forming a swirl pattern, and once a particular point on the wafer entered the solution, it stayed immersed. While these results can be achieved without rotating the wafer during immersion, some rotation is required to eject any small air bubbles from the wafer surface that may have been entrained.

Figure 7: Modeling of wetted area using parameters that eliminate the swirl pattern.

Results of the Improvements. After the wafer entry conditions were modeled, changes in z-speed and wafer rotation speed were implemented to eliminate the swirl pattern and achieve uniform wetting conditions. At the same time, a new clamshell-style wafer carrier was introduced that reduced overall chemical displacement and enabled optimum operation under the new conditions. The investigators confirmed that the swirl pattern was also eliminated on patterned wafers, as shown in Figure 8. Finally, a corresponding improvement in overall defectivity was achieved, eliminating a key yield detractor. Figure 9 demonstrates that after the changes were implemented, pit defects on product wafers were eliminated.

Figure 8: Defect results on patterned wafers showing the elimination of the swirl pattern.
Figure 9: Copper pit defects on actual product wafers before and after implementation of the plating process modification.


With the availability of improved defect metrology tools for plated copper films, several defect types specific to plating have been identified. Although not all of these defect types affect yields, they can be a nuisance because they overwhelm analysis and make identification of true yield-limiting defects more challenging. While chemistry and process plating conditions can reduce overall defect counts significantly, this work focused on eliminating a fundamental defect mode by altering how the wafer enters the plating cell. By modeling the formation of the signature swirl defect and changing the wafer entry parameters (rotation rate and entry speed), uniform wetting was achieved, resulting in the elimination of the defect type.


1. J Reid et al., “Optimization of Damascene Feature Fill for Copper Electroplating Process,” in Proceedings of the International Interconnect Technology Conference (Piscataway, NJ: IEEE, 1999), 284–286.

2. JP Lu et al., “Understanding and Eliminating Defects in Electroplated Copper Films,” in Proceedings of the International Interconnect Technology Conference (Piscataway, NJ: IEEE, 2001), 280–282.

Ted Cacouris, PhD, is the product management director for the Novellus Electrofill business unit in Tualatin, OR. He has been in the business unit for 10 years, starting with the team that developed copper technology. Previously, Cacouris worked at IBM as a process engineer and at Intel as an integration engineer. He received a PhD in electrical engineering from Columbia University in New York City. (Cacouris can be reached at 503/685-8366 or

Chee Ping Lee is a field process engineer for Novellus Singapore. He has two years of experience in the semiconductor industry, primarily in the area of high-density plasma chemical vapor deposition and electrocathodic plating processes and equipment. He received a BEng degree in chemical engineering from the National University of Singapore. (Lee can be reached at +65 94577555 or

Augustine Teo is a program manager for metal products at Novellus Singapore. With six years of experience in the semiconductor industry, he has focused mainly on copper physical vapor deposition, electroplating, and copper CMP. He received a BEng degree in materials engineering from the Nanyang Technological University in Singapore. (Teo can be reached at +65 96270272 or

Li Chaoyong, PhD, is a process manager in the thin-film department at Chartered Semiconductor in Singapore. He has more than 17 years of experience in the semiconductor industry. He received a bachelor’s degree in device physics, a master’s degree in materials science, and a PhD in electrical and electronics engineering. (Chaoyong can be reached at +65 97401798 or

He Xin is a senior process engineer at Chartered Semiconductor. He has more than seven years of experience in the semiconductor field. He received a bachelor’s degree in electronics engineering from Huazhong University of Science and Technology in Wuhan, China, and a master’s degree in electrical engineering from Nanyang Technological University in Singapore. (Xin can be reached at +65 93385978 or

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