If you want to improve CD control, you must
identify sources of focus and dose errors
Chris A. Mack
Linewidth or critical dimension (CD) control generally means ensuring that the widths of certain critical features, measured at specific points on those features, fall within acceptable bounds. Since linewidth control will affect device performance in a layer-specific manner, two examples—gates and contacts/vias—will be discussed here.
Why Is CD Control Important?
The classic example of the influence of CD control on device performance is at the polysilicon gate level of standard CMOS logic devices, as shown in Figure 1.1 Physically, the polysilicon gate linewidth controls the electrically important effective gate length, which is directly proportional to the switching time of the transistor. Thus, narrower gates tend to make transistors that can switch on and off at higher clock speeds. But smaller is not always better. Transistors are designed for a specific gate length. As the gate length gets smaller than this designed value, the transistor begins to “leak” current when it should be off. If this leakage current becomes too high, the transistor is judged a failure.
Figure 1: A distribution of polysilicon gate linewidths across a chip can lead to different performance failures. Tightening up this distribution allows for a smaller average CD and faster device performance.
When printing a chip with millions of transistor gates, the gate lengths take on a distribution of values across the device. This across-chip linewidth variation produces a range of transistor behaviors that affects the device’s overall performance. As a signal propagates through the transistors of a chip to perform some operation, there will be several paths, connected chains of transistors that operate in parallel and interconnect with each other. The overall speed with which the operation can be performed (i.e., the fastest clock speed) is limited by the slowest (largest gate CD) transistor in the critical path for that operation. On the other hand, because of leakage current, the smallest gate CD on the device limits the device’s reliability. If too many transistors on the chip have small gate CDs, the higher leakage current can result in unacceptably high power consumption.
Table I: Examples of random focus errors (µm, 6σ total range) for different lithographic generations.2,3
A tighter distribution of polysilicon gate CDs will result in reduced timing errors. This smaller range of linewidths also means that the average linewidth can be reduced without running into the leakage current limit. As a result, the overall speed of the chip can be increased without having a negative impact on reliability. The resulting improved bin sort—the fraction of chips that can be put into the high-clock-speed bins when the device goes through final test—can provide significant revenue improvements for the fab.
Table II: Examples of systematic (µm, total range) and random focus error estimates combined to determine the built-in focus errors (BIFE) of a process.2,3
Like transistor gates, the impact of errors in a contact hole or via CD differs for oversized versus undersized contacts. If a contact hole gets too big, the hole can overshoot the edge of the pattern below which it is making contact, causing an electrical short circuit. If a contact hole gets too small, the electrical contact resistance will increase. Contact resistance is proportional to the contact area, and thus to the square of the contact diameter. A 10% error in contact CD causes a roughly 20% error in contact resistance. If the contact/via resistance gets too high, signals propagating through that contact/via will slow down. For voltage-sensitive parts of the circuit (such as the source/drain contacts), the voltage drop across the contact can change the device’s electrical characteristics.
How Can CD Control Be Improved?
Fundamentally, errors in the final dimension of a feature are the result of errors in the tools, processes, and materials that affect the final CD. An error in a process variable propagates to become an error in the final CD based on the various physical mechanisms by which the variable influences the lithographic result. In such a situation, a propagation of errors analysis can be used to help understand the effects. Suppose the influence of each input variable on the final CD were expressed in a mathematical form:
CD = ƒ(v1,v2,v3,...).
Here, vi represents the input (process) variables. Given an error in each process variable Δvi, the resulting CD error can be computed from a Taylor expansion of the function. If the errors in the process variables are small (hopefully, this is true), we can ignore the higher order and cross terms of the expansion to leave a simple, linear error equation:
Each Δvi corresponds to the magnitude of a process error. Each partial derivative ∂CD/∂vi represents the process response, the response of CD to an incremental change in the variable. This process response can be expressed in many forms; for example, the inverse of the process response is called process latitude.
The linear error equation can be modified to account for the nature of the errors at hand. In general, CD errors are specified as a percentage of the nominal CD. For such a case, the goal is usually to minimize the relative CD error, ΔCD/CD. Additionally, many sources of process errors result in errors that are a fraction of the nominal value of that variable. For example, illumination nonuniformity in a stepper produces a dose error that is a fixed percentage of the nominal dose. For such error types, one should modify the second equation to use a relative process error, Δvi/vi.
Although the second and third equations may seem obvious, even trivial, in their form, they reveal a very important truth about error propagation and CD control. There are two distinct ways to reduce ΔCD: reduce the magnitude of the individual process errors (Δvi), or reduce the response of CD to that error (∂CD/∂vi). The separation of CD errors into these two source components identifies the two important tasks that face the photolithography engineer. Reducing the magnitude of process errors is generally considered a process control activity, while reducing the process response is a process optimization activity. Often, these two activities are reasonably independent of each other.
Sources of Focus and Dose Errors
Focus errors arise from many sources, both random and systematic. Tables I and II list estimates of the focus errors by source for different lithographic generations: a 1991 0.5-µm i-line process, 1995 0.35-µm i-line and krypton fluoride (KrF) stepper processes, a 0.18-µm KrF scanner process, and a modern 90-nm argon fluoride (ArF) process.2,3 The values shown are typical but certainly vary from process to process. Although the tables are reasonably self-explanatory, a few items are worth noting. Errors in flatness or tilt on the mask are reduced by the reduction ratio of the imaging tool squared (assumed to be 4× in this example). Wafer flatness is a total range over the exposure field, assuming autoleveling is turned on. One of the scanner’s primary advantages is that the exposure slit sees a smaller region of the wafer and thus has a smaller focus error because of wafer nonflatness compared with a stepper, even for the same wafer.
Systematic focus errors include wafer topography (although chemical-mechanical polishing has proven its worth, it is not quite effective enough to make wafer topography a negligible problem), lens aberrations across the field or slit, and the errors caused by focusing through the thickness of the resist. When one combines all of these error sources, an estimate of the total built-in focus errors (BIFE) of the process can be obtained. While not considered here, phase errors on a phase-shift mask can also act like a focus error.
Filling in the values in tables such as the two presented here serves two important functions. First, an evaluation of the BIFE can be combined with a measurement of the focus-exposure process window for the target process to see whether the process capability (the process window) exceeds the process requirements (such as the BIFE). Second, a listing of sources of focus errors inevitably leads to ideas where improvements can be made. The largest sources of errors, such as wafer nonflatness and wafer topography, offer the greatest potential for improvement.
Many errors that are not focus errors but still affect CD can be thought of as equivalent to an exposure dose error. Typical examples of those include:
• Across-field (slit) intensity nonuniformity.
• Field-to-field and wafer-to-wafer dose control.
• Resist sensitivity variations (including development process variations).
• Resist/bottom antireflective coating thickness variations (reflectivity variations).
• Postexposure bake temperature variations.
• Flare variations.
• Mask CD nonuniformity.
Smaller feature sizes have necessitated tightened requirements for dose control. For the 0.5-µm generation, the built-in dose errors of a well-controlled process averaged 15% (range). At the 90-nm node, dose errors are typically less than about 6%.
CD control ranks as one of the most important metrics of the lithography process. While it is common to apply the rule of thumb that CDs are allowed to vary no more than ±10%, a better understanding of the impact of CD errors on device yield and performance allows for more-effective decision making with regard to CD control. The CD variation problem can be divided into two tasks: process optimization (reducing the sensitivity of the final CDs to variations in the process) and process control (reducing the magnitude of process errors). Both of these tasks are better accomplished after completing a systematic inventory of existing process errors for the targeted processes and layers.
1. J Sturtevant et al., “Characterization of CD Control for sub-0.18 µm Lithographic Patterning,” in Optical Microlithography XII, Proceedings of SPIE, vol. 3679 (1999), 220–227.
2. CA Mack, “Understanding Focus Effects in Submicron Optical Lithography, Part 3: Methods for Depth-of-Focus Improvement,” in Optical/Laser Microlithography V, Proceedings of SPIE, vol. 1674 (1992), 272–284.
3. S Sethi et al., “Lithography Strategy for Printing 0.35-µm Devices,” in Optical/Laser Microlithography VIII, Proceedings of SPIE, vol. 2440 (1995), 619–632.
Chris A. Mack, gentleman scientist, was vice president of lithography technology for KLA-Tencor from 2000 to 2005. He now writes and consults in Austin, TX (contact: email@example.com).
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