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INDUSTRY NEWS

FEOL challenges, new materials push surface-preparation agenda

SUPERFICIALLY SPEAKING: FEOL processes present daunting cleaning challenges as device features become more fragile. (PHOTO COURTESY OF FSI INTERNATIONAL)

To batch clean or not to batch clean? Of the many wafer cleaning questions facing a semiconductor industry in flux, this is one of the most pressing. The introductions of exotic materials and increasingly delicate device features have chipmakers and suppliers searching from the front to the back end for the right surface-preparation answers.

That search presents many difficulties. The growing use of high- and low-k dielectric materials as well as the parallel emergence of new gate-stack metals in place of polysilicon in order to minimize leakage and maximize transistor speed pose several key challenges, industry experts say.

Some of the preeminent challenges are in FEOL processes, says Steven Verhaverbeke, chief technology officer in wet cleans for Applied Materials. “One of the first [challenges] in the front end is to clean without damaging features.” The problem occurs in two instances—the first coming after shallow-trench isolation (STI) etching, the second after etching the gate.

“So far, nobody has come up with a really conclusive solution in the front end. The wet benches have been dominant for cleaning, but in batch, nobody can clean without damage,” explains Verhaverbeke, fresh from his appearance on a panel at a Sematech surface-preparation and cleaning conference in early May. To protect their product, device manufacturers “turned off the megasonics and cleaned at those two steps without damage and also without much cleaning efficiency.”

Although workable, this method is not ideal, Verhaverbeke points out, and the cleaning inefficiency challenges fab engineers to keep their processes as pristine as possible. “You basically optimize the process to make sure that the etch reactor does not leave too many particles…from the previous steps, mostly the etch step.” Particles from plasma nucleation, for instance, settle on the wafer. And this problem is the force behind what the technology officer sees as a growing trend.

“That’s going to drive a conversion from batch to single-wafer [cleaning],” he believes. “That challenge is much easier to address in a single wafer, because you can focus on one wafer, and you can clean with only very precise power, just enough to remove the particles.”

Throughputs with a theoretical maximum of 240 wafers per hour are possible because most single-wafer tools feature eight chambers, each processing 30 wafers per hour. “In reality, you’ll probably be below that, probably [an acceptable] 150 to 180 wafers per hour.”

George Petricich, vice president of product marketing for DNS Electronics, says the nature of particle removal on single-wafer systems gives them a leg up on their batch counterparts. “In additon to processes such as bevel etch that are unique to single-wafer processing, customers are migrating to single-wafer cleans to avoid particle deposition, which is an inherent factor in batch processing. This is especially true for contaminants removed from the back and bevel of the wafer.”

Still, it’s inconclusive whether single-wafer cleaning will become the option of choice in FEOL processes, says Raj Jammy, an IBM assignee who directs the front-end processes division at Sematech. “I can’t confidently say yes or no. There is always going to be a certain segment of the industry that will need batch wafer processes, and there will be certain applications or certain specific cases where single-wafer makes a lot of sense.”

This horses-for-courses approach means memory device manufacturing, for instance, will call for bulk etch, while high-end logic or ASIC manufacturing, “where you need a certain type of interface control before you put down materials,” calls for a single-wafer tool, Jammy explains.

“Fabs are constantly challenged with the compromise between cleaning efficiency versus pattern damage,” Petricich says. “Essentially, you’d like to have 100% particle-removal efficiency, but that’s a big challenge as IDMs progress to smaller and smaller geometries and increasing aspect ratios. DNS is aggressively introducing new batch and single-wafer cleaning technologies to expand process windows.”

Screen has covered its bases with two products, says the executive, adding, “In essence, we compete with ourselves.” The company’s FC-3000 is a single-bath wet station for cleaning 300-mm wafers, and its MP-2000 spin processor features a single-chamber processing system.

Materials manufacturers are adapting as well. “Certainly, FEOL is someplace where we’re seeing activity in a way that we haven’t seen it before,” states Michael Fury, vice president of R&D and engineering for DuPont EKC Technology. “The back end historically has been where custom-formulated products like ours were used, simply because the front end always stood up to brute force.”

Two schools of thought have emerged, he explains. “One seems to be to try to take dilute HF and stretch that as far as possible. The other is to quickly recognize that that [approach] will run out of steam and that there’s probably value in starting to learn how to formulate for the front end just like we did the back end.”

Chipmakers in one geographic region in particular are doing just that. “I’d be remiss not mentioning that since about 2003, the majority of EKC’s specialty chemicals business has shifted into the Asia/Pacific region,” Fury says. In fact, he points out that the bulk of the sales come not from Japanese clients but from customers in Taiwan, China, Singapore, Malaysia, and South Korea. He credits rapid expansion of the foundry and DRAM businesses. Samsung is “going gangbusters,” and both TSMC and UMC “are just driving huge volumes.” In addition, many fabs are opening in China. EKC has responded to this bustle of activity by opening an applications lab in Hsinchu, Taiwan.

“I don’t think we’ve hit the peak yet for single-wafer installations. There are still a lot of batch [cleaners] being put into the new facilities,” Fury adds.

“The Asian markets embraced single-wafer cleaning earlier than the United States,” agrees Petricich. The industry is seeing fewer batch tools and more single-wafer tools used in BEOL processes at the 90-nm node, he says, and the trend is “extremely prevalent at 65 nm. FEOL migration is happening one to two technology nodes behind BEOL.”

The reasons for the faster adoption rate in the Asia/Pacific region vary. Based on his work with a foundry in Taiwan, Ian Brown, a senior product applications engineer with Tokyo Electron’s surface-preparation systems group, believes single-wafer systems offer process flexibility not available in a batch tool. “Also, I guess so many manufacturers are trying to rush as fast as they can, trying to get an edge.” Brown, who presented a paper on a novel chemical oxide-removal process at the Sematech conference, notes that TEL “did really well in Taiwan last year in terms of surface-preparation products.”

“In the back end, single-wafer cleaning has already taken over most of the processes, and in the front end it’s just starting now,” Applied’s Verhaverbeke says. He says the shift to the front end among Asia/Pacific manufacturers is no more prevalent than it is among European producers. “The front-end leaders are actually in Europe. They’ve basically been proponents of single-wafer for front-end cleaning for a long time.”

And U.S. device makers? “They’re behind the curve converting to front end, no doubt,” Verhaverbeke replies. “I don’t know why. Perhaps they’re focused on other things.” He suggests that U.S. manufacturers have had their eyes trained more on high-k materials and copper to the exclusion of surface-preparation concerns.

With scaling pushing the degree of difficulty even further, Petricich and others emphasize that selectivity is a watchword. That capability becomes particularly acute when IDMs are paying “more than $3 billion to put a wafer fab in place,” says Alex Oscilowski, Sematech’s vice president of strategy. In a presentation on the economic barriers to nanotechnology R&D at the consortium’s recent cleaning conference, he insisted that “it’s absolutely vital to get the right return on the investment.” The economic challenges are just as daunting as the technological ones, and R&D money must be wisely spent so that the right technology finds its way into these costly factories.

Collaboration between suppliers and semiconductor manufacturers is vital to this effort, Oscilowski insists. Partnerships will help ensure that cost-effective processes are built into the R&D effort at the beginning. As one example, he cites the introduction of high-k dielectric materials and metal gates “and all the different cleans going forward in that area.”

In the gate stack alone, “there are a multitude of cleaning steps and technologies necessary,” the Sematech executive notes. For dual-metal-gate transistors, process engineers “have to deal with two different metals and different selectivity. How do you manage that in a cost-effective way?” The gate stack also presents challenges in the source drain area as well as in cleaning and anneals before high-k deposition.

“So there are at least three aspects within this high-k metal gate-stack type of technology where cleaning is going to be absolutely crucial, and cleaning is a step that doesn’t get thought of as…fundamental and necessary,” he continues. “There’s a big opportunity for getting more-cost-effective processes that have to be built into R&D up front.”

Another challenge is the shift in cleaning chemistries, where “a lot is still being worked out,” says Jeffery Butterbaugh, chief technologist for FSI International and the cochairman of the Front-End Process technology working group for the International Technology Roadmap for Semiconductors (ITRS). Delaying the introduction of high-k metal gates “puts pressure on some of the other device parameters.”

“I think it’s going to drive the need for low-k material-cleaning processes a little further out,” explains Butterbaugh, who delivered an opening-day FEP overview at the Sematech conference. “Without high-k, metal gate junctions are going to be shallower for a while.” With selectivity a key concern, the question is, “How do you clean the surface without etching the silicon?”

Regarding collaboration and his role as an FEP group cochairman, Butterbaugh mentions that memory manufacturers “are a little less forthcoming” sharing information on their processes, while logic device manufacturers, for instance, “are a little more open.” He attributes the tight lips to a “cutthroat” memory market that “moves pretty quickly and has pretty slim margins.” Some logic device manufacturers can be just as reticent, he notes. As a result, “it’s kind of hard to do roadmapping and project solutions when some of the people working in this area are reluctant to talk about what they’re doing.”

Butterbaugh says the fact that some new material introductions have been pushed up has helped the supplier of surface-conditioning equipment. The industry is finding unique ways to develop better workarounds. For years, porous low-k was on the roadmap, and the industry found a way to work with interconnect design and squeeze more from the design guys. “Trying to integrate porous low-k into BEOL is going to be a real challenge, and it affects cleaning solutions. It’s not necessarily a positive development,” Butterbaugh notes.

“It’s been very difficult for the industry to make that investment and not have a return on it,” Butterbaugh continues. Specifically, he points to money poured into the supercritical CO2 cleaning process over the past five years. That effort has been “really shut down now,” and the focus has shifted to porous low-k.

FSI recently introduced its ViPR technology as a technique for wet photoresist stripping without ashing, according to Butterbaugh. The technique eliminates approximately 80% of ashing steps in FEOL processes, up from 30–40%.

The technology eliminates the need for ashing on most implanted-resist-stripping steps, the company says. The technology is available for FSI’s Zeta G3 spray cleaning platform. As the use of implanted resist in semiconductor manufacturing continues to rise, the amount of permissible material loss and surface damage has decreased. This need will become more acute as semiconductor manufacturing reaches the 65- and 45-nm technology generations.

“Actually, there are some photoresists we can’t remove, even with ashing,” Butterbaugh points out. FSI and others are trying to find methods to solve this problem, including the use of the standard sulfuric acid and HP mixture.

Applied’s Verhaverbeke says the back end is becoming more difficult to clean with the introduction of the latest low-k materials. In particular, resist stripping without damage has become hard to do. “The photoresist is organic and the low-k is organic, so selectivity is an issue,” he says. That process is being tweaked. Since the photoresist ash is becoming less aggressive, the clean is left with a higher burden to remove the residue. Suppliers are developing new solvents to address that burden, he adds.

“Another issue is the fact that if you ash the photoresist less aggressively, the low-k, which is intrinsically hydrophobic, stays hydrophobic,” Verhaverbeke points out. “The fact that it becomes hydrophilic during ash is an indication that you damaged it.”

A Marangoni-style cleaner for the process back end is an efficient solution, he says. “Marangoni immerses the whole wafer. We don’t care if the surface is hydrophobic or hydrophilic. Once it’s immersed, the wafer doesn’t care about that.”

Unlike the batch-versus-single-wafer debate, Verhaverbeke insists that the wet-versus-dry question on wafer cleaning is settled. “The dry definitely lost the ring, I would say. There still may be an application for dry in only a few applications for removing oxide layers. But for the rest, it has basically disappeared from the scene.” —JC


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