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Using an STI gap-fill technology with a high-aspect-ratio process for 45-nm CMOS and beyond

Armin T. Tilke, Roland Hampp, Chris Stapelmann, and Marcus Culmsee, Infineon Technologies; Richard Conti and William Wille, IBM Microelectronics; and Rakesh Jaiswal, Maria Galiano, and Alok Jain, Applied Materials

High-quality SiO2 has always been the dielectric of choice for isolation between active devices. For CMOS nodes below 180 nm, shallow-trench isolation (STI) is the preferred electrical isolation scheme. The STI fill consists of SiO2 deposited using either high-density plasma (HDP) or thermal chemical vapor deposition (CVD) based on an ozone (O3)/TEOS chemistry.1 HDP has been the more attractive option because of its good gap-fill capability, better as-deposited film properties, and higher throughput. However, the use of HDP is making it increasingly difficult to provide good gap fill for technology nodes <65 nm with aspect ratios >8:1. To fill STI geometries with high aspect ratios, ex situ or in situ back etches must be introduced in conjunction with the HDP process to ensure void-free fills. However, this method has drawbacks: It increases process complexity and results in liner attack during the back-etch and deposition steps, limiting the choice of STI liners.

In the present work, a high-aspect-ratio process using a new O3/TEOS–based CVD process was implemented to perform STI gap fill in sub-65-nm CMOS applications. This article is based on work that was performed at the IBM Microelectronics Div. Semiconductor Research & Development Center in Hopewell Junction, NY, as part of the Logic Development Alliance between IBM, Chartered Semiconductor, Infineon Technologies, and Samsung (ICIS).

Device Fabrication and Process Integration

The work described in this article deals with a high-aspect-ratio STI fill process with tensile stress.2 The process was developed using an O3/TEOS–based subatmospheric CVD process at 540°C. The technology has two key benefits: gap-fill capability for aspect ratios >10:1 and a high deposition rate. Figure 1 shows the process’s key parameters. To ensure optimized nucleation at the start of deposition, a thin nucleation layer is first deposited using ultrahigh O3/TEOS ratios of 200:1. After a TEOS ramp, the remaining part of the deposition step is performed using a high-productivity, high-TEOS flow process.

Figure 1: TEOS flow and spacings during high-aspect-ratio deposition. During the deposition of the nucleation layer, the O3:TEOS ratio is very high (step 1). After TEOS ramp, the cap of the fill is deposited with high productivity.

Since high-aspect-ratio deposition does not use plasma, liner attack does not occur. Therefore, a variety of liners, including SiO2/thin Si3N4 or SiON, can be used without running the risk of corner clipping during fill. A dedicated STI preanneal step after deposition serves to reduce the wet etch rate and moisture absorption. Figure 2 compares typical process flows for HDP and high-aspect-ratio processing.

Figure 2: Schematic diagram of HDP fill and high-aspect-ratio processing (HARP).

To compare the material properties of high-aspect-ratio processing and HDP, the wet etch rates were determined using dilute hydrofluoric acid and buffered hydrofluoric acid chemistries in the ICIS 45-nm CMOS process flow, as detailed in Table I. The high-aspect-ratio film was preannealed at 1050°C for 30 minutes in dry N2 ambient, and both the high-aspect-ratio and the HDP fill were postannealed using a conventional high-temperature furnace anneal.

Table I: Wet etch rates for HDP and high-aspect-ratio processing (compared with thermal oxide) using dilute hydrofluoric acid and buffered hydrofluoric acid.

Figure 3 presents the active width loss for different wet and dry anneals for high-aspect-ratio STI structures with and without a nitride liner. During the anneal process, oxidation of the active regions between two trenches can take place because of the remaining excess oxide and moisture inside the high-aspect-ratio fill. For steam annealing without an Si3N4 liner, the active width loss is about 12 nm. Therefore, an Si3N4 liner is recommended whenever a steam anneal is used.

Figure 3: Active width loss in shallow trenches from wet and dry anneal processes (a) without and (b) with a nitride liner. Without a nitride liner, active width loss is significant during steam annealing, since further oxidation takes place during the anneal.

To investigate the film stress of the high-aspect-ratio fill, the stress-temperature curve for blanket wafers after STI deposition at 540°C was measured, as illustrated in Figure 4. As the temperature was increased to 600°C, the film became highly tensile. When the temperature was raised to 900°C and then reduced to room temperature, the film became compressive.

Table II: Trench dimensions and aspect ratios for different bulk CMOS technology nodes.
Figure 4: Stress-temperature curve for blanket wafers that underwent 540°C high-aspect-ratio deposition.

During a high-temperature anneal, the shrinking of the high-aspect-ratio film in the STI trench causes strain in the device regions. Strain engineering, it appears, enables the high-aspect-ratio film in the trench to remain tensile even under high-temperature anneal conditions and subsequent cooling because the film is confined to the trench.

To investigate high-aspect-ratio film stress on structured wafers, in-line stress measurements were performed using wafer bow tests after both HDP and high-aspect-ratio processing under various dry annealing conditions (1050° and 950°C) with and without an Si3N4 liner. The measurements were performed on as-deposited films after the STI preanneal step for the high-aspect-ratio groups and after CMP and the STI postanneal step for both the high-aspect-ratio and the HDP groups.

To deduce film stress from the wafer bow, oxide film thickness must be known. Hence, the high-aspect-ratio film shrinkage of about 6% was taken into account. For the measurements performed after CMP and the STI postanneal step, mean oxide film thickness was assumed to be 70% of the STI fill height, since that value roughly corresponds to the total STI area on the wafer.

While these approximations compelled the investigators to take the absolute stress values of the post-CMP measurement with caution, a clear trend emerged. As deposited, HDP is highly compressive, while high-aspect-ratio processing results in a slightly tensile film, as illustrated in Figure 5a. After the high-aspect-ratio preanneal step, the high-aspect-ratio films become compressive, as shown in Figure 5b. With higher anneal temperatures, the stress increases, and the nitride liner has only a minor effect on film stress. HDP remains compressive after CMP and the STI postanneal step, whereas the high-aspect-ratio fills become tensile, with the 1050°C group having less stress than the 950°C group, as shown in Figure 5c. Thus, STI film stress can be tuned broadly under different high-aspect-ratio annealing conditions.

Figure 5: In-line stress measurements for HDP and high-aspect-ratio processing under different annealing conditions with and without a nitride liner. The measurements were performed (a) as deposited, (b) after the STI preanneal for the high-aspect-ratio groups, and (c) after CMP and STI postanneal.

To test the gap-fill performance of high-aspect-ratio processing, trenches with dimensions similar to 45- and 32-nm STI ground rules were fabricated, which are listed in Table II. Figure 6 shows a cross-sectional scanning electron micrograph (SEM) of such trenches. Neither top-down inspection after CMP nor cross-sectional microscopy indicated the presence of voids in any of the trenches investigated here, which had aspect ratios as high as ~12:1.

Figure 6: Image showing minimum STI feature sizes filled using high-aspect-ratio processing.

While the high-aspect-ratio process enables users to choose from a variety of liners, pure oxide liner is not suitable for very narrow devices because of the out-diffusion of boron into the STI fill, which worsens rolloff. However, alternatives include either a very thin nitride liner (<5 nm thick) to avoid divot formation or an oxynitride liner, both of which suffer from liner attack during conventional HDP fill. Three liner types are presented in the SEM images in Figures 7a–c: a conventional oxide/nitride liner, an oxide/nitride liner with a nitride thickness below ~4 nm, and an oxynitride liner formed through reoxidation of the 4-nm nitride liner. All three types remain physically intact after high-aspect-ratio fill.

Figure 7: Images showing STI with (a) a conventional oxide/nitride liner, (b) oxide/nitride in which the nitride thickness was ~4 nm, and (c) an oxynitride liner that was produced by reoxidizing the 4-nm nitride liner. All trenches were filled using high-aspect-ratio processing.

Electrical Results

To determine the performance of the high-aspect-ratio process, device data were obtained using relaxed 65-nm CMOS and isolation structures. Both data types showed that the process did as well as or better than the HDP reference process.

Figure 8 shows the Ioff (leakage) versus Ion (current) curves for wide (10 × 1-µm) and a narrow (20 × 0.12-µm) n- and p-FETs. The high-aspect-ratio fill changed the threshold voltage narrow-width-rolloff behavior of the n-FET slightly. For both the narrow and the wide FETs, most of the Ioff /Ion data differences between the high-aspect-ratio and HDP devices can be attributed to that effect. In contrast, p-FET rolloff turned out to be very similar for the high-aspect-ratio and HDP groups. Thus, the p-FETs are better suited for directly comparing device performance than the n-FETs.

Figure 8: Ioff/Ion data for (a) a wide p-FET, (b) a narrow p-FET, (c) a wide n-FET, and (d) a narrow n-FET that were processed using either HDP or high-aspect-ratio STI fill. The narrow p-FET showed an Ioff/Ion improvement of ~10%.

While the data for the wide p-FET presented in Figure 8a indicate a relatively insignificant Ioff /Ion performance gain, the data for the narrow p-FET presented in Figure 8b show a significant Ioff /Ion performance increase of about 10%.

Figure 9 schematically compares STI stress on the device channel region of narrow versus wide devices. For narrow devices, the stress perpendicular to the channel (parallel to the gate) dominates over the stress parallel to the channel (perpendicular to the gate). For wide devices, the reverse is the case—the stress parallel to the channel dominates.

Figure 9: Schematic diagrams comparing STI stress parallel to and perpendicular to the FET channel for a narrow and a wide device.

The compressive STI stress of the HDP fill perpendicular to the p-FET channel decreases p-FET performance, thus increasing Ioff versus Ion. With the tensile STI stress resulting from the high-aspect-ratio fill process, the narrow p-FET has the highest performance gain. Since the tensile stress parallel to the channel should improve n-FET performance, this effect should be most pronounced in the wide n-FET. In fact, the data for the wide n-FET shown in Figure 8c indicate a slight performance increase for the high-aspect-ratio group compared with the HDP reference group. In contrast, the data for the narrow n-FET that underwent high-aspect-ratio processing shown in Figure 8d are clearly worse in terms of Ioff /Ion because of the changes in threshold voltage. Taking that into account and gauging the Ioff /Ion of the wide n-FET would lead to a distinct performance gain for that wide device.

Figure 10 compares the yield of a 4-Mbit SRAM array fabricated using HDP versus high-aspect-ratio processing. With a cell size of 0.54 µm2, the 65-nm SRAM had aggressive dimensions and minimum trenches of approximately 60 nm between the liners, for an aspect ratio of ~7:1. When conventional HDP fill was used to fabricate the device, the array yield suffered from hard failures resulting from fill voids and shorts between adjacent FETs. The spread between the best and the worst wafer in this test group was very large, indicating that the fill was at the edge of the process window. The use of high-aspect-ratio processing nearly doubled the yield, drastically reducing the spread between the best and worst wafers.

Figure 10: Yield comparison for SRAM devices fabricated using HDP versus high-aspect-ratio fill.


This article has demonstrated that good gap-fill performance can be attained in structures with high aspect ratios. Since neither sputtering nor dedicated in situ or ex situ back etch are needed during high-aspect-ratio fill, liner attack is not observed. This phenomenon has enabled engineers to choose from a wide range of liners.


This article is an edited version of a paper that was presented at the IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), held May 22–24, 2006, in Boston. The authors would like to thank Dirk Vietzke from Infineon Technologies in East Fishkill, NY, for providing the SEAM yield data. They also wish to acknowledge Manfred Eller from Infineon for performing the device evaluation. Finally, they would like to thank Applied Materials in Santa Clara, CA, for performing the high-aspect-ratio deposition work.


1. A Bryant, W Hansch, and T Mii, “Characteristics of CMOS Device Isolation for the ULSI Age,” Electron Devices Meeting, Technical Digest, International (1994): 671–674.

2. R Arghavani et al., “Stress Management in Sub-90-nm Transistor Architecture,” IEEE Transactions on Electron Devices 51, no. 10 (2004): 1740–1743.

Armin T. Tilke, PhD, is senior engineer for CMOS development at Infineon Technologies in East Fishkill, NY. He belongs to the ICIS alliance for 65- and 45-nm CMOS integration. From 1999 to 2003, he worked at Infineon Technologies in Munich and Dresden in the BiCMOS technology development department. In 2004, he worked on novel embedded flash integration. He has published about 30 articles and conference presentations in the field of silicon nano- and microelectronics. He received a diploma degree in physics from the Technical University and a PhD in applied semiconductor physics from the Ludwig Maximilian University/Center for Nanoscience, both in Munich. (Tilke can be reached at

Roland Hampp is responsible for dielectric and metal deposition processes at Infineon Technologies. He also belongs to the ICIS development alliance. He began his career 10 years ago at Siemens Semiconductors in Regensburg, Germany, and Munich as a unit process engineer for metal fill processes. He received a master of science degree for microsystems technology from the University of Regensburg. (Hampp can be reached at

Chris Stapelmann is a technology lead engineer and Infineon assignee at IMEC in Leuven, Belgium. He has worked in the semiconductor industry for eight years, first at Novellus and then as a systems expert at Infineon Technologies in Richmond, VA. Then he spent two years as a process engineer at Infineon’s facility in East Fishkill, NY. He received a diploma degree from the Rheinisch-Westfälische Technische Hochschule in Aachen, Germany, where he focused on material science. (Stapelmann can be reached at

Marcus Culmsee, PhD, is a senior engineer at Infineon Technologies and a member of the ICIS alliance in 65-nm technology development at the IBM Semiconductor Research and Development Center in East Fishkill, NY. He received a diploma degree in chemistry and a PhD in natural science from the University of Cologne in Germany. (Culmsee can be reached at

Richard Conti is a senior process development engineer at the IBM Semiconductor Research and Development Center in East Fishkill, NY. He has been a manufacturing and development project leader in the area of thin-film deposition. Conti is the author of several papers on chemical vapor deposition in semiconductor processing, and he holds numerous patents in this area. He received a BS in chemical engineering from the Polytechnic Institute of New York in New York City and an MS in chemical engineering from the Massachusetts Institute of Technology in Cambridge. (Conti can be reached at

William Wille focuses on R&D at IBM Microelectronics at the IBM R&D center in East Fishkill, NY. He started his career at Fairchild Semiconductors and then joined IBM in 1983. He has held process engineering positions primarily in the area of reactive ion etch. He has also held managerial positions. He received a BS in biochemistry and an MS in materials science from the University of Cincinnati in Ohio. (Wille can be reached at

Rakesh Jaiswal leads a process engineering group at Applied Materials in Singapore. He has more than 10 years of industry experience, the last six of which he has spent at Applied Materials in the areas of etch and CVD up to the 45-nm technology node. The author of semiconductor-related papers in conference proceedings, he received an MS in physics and a master of technology degree in solid-state materials from the Indian Institute of Technology in Delhi. (Jaiswal can be reached at

Maria Galiano has worked at Applied Materials for the past 16 years in various engineering and managerial positions. She has focused primarily on dielectric CVD. She received a BS from the Massachusetts Institute of Technology in Cambridge and an MS from the University of California at Berkeley, both in materials science and engineering. (Galiano can be reached at

Alok Jain is a process technologist and a member of the technical staff at Applied Materials. He focuses primarily on process development and integration of FEOL products. He received an MS in manufacturing systems engineering from the Asian Institute of Technology in Klong Luang, Pathumthani, Thailand. (Jain can be reached at

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