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Tech Emergent

Hu takes up the battle cry of CMOS ‘rejuvenation’

Chenming “Calvin” Hu believes more emphasis should be placed on research into technologies that can rejuvenate, enhance, and extend CMOS, rather than overemphasizing efforts to replace the existing chip-processing infrastructure. Hu is the TSMC distinguished chair of microelectronics in the department of electrical engineering and computer sciences at the University of California, Berkeley. The award-winning educator is a prolific researcher and technical-paper writer, and is recognized as one of the foremost experts in FinFETs and IC simulation. A few weeks after I heard Hu’s “From CMOS to NanoCMOS” keynote at the recent Advanced Semiconductor Manufacturing Conference, I talked with him about his views on some of the emerging technologies that will extend the lifetime of CMOS chipmaking. — Tom Cheyney

MICRO: You have talked about this idea of rejuvenating, not replacing, CMOS with new technologies. Could you explain what you mean by that?

HU: The CMOS technology is no stranger to difficulties and barriers. If we look back at the history of CMOS, one can easily list a dozen problems that at one point or another were considered to be total showstoppers, including the cost of building fabs. At one time, we all remember a billion dollars was considered an unattainable sum for the industry to raise to build the fab. Today, we see that some people are lamenting that there are too many of these billion-dollar fabs being built.

Another example is power. The power problem is not new. It reached a crisis point in the late 1980s and early 1990s, and the industry managed to surpass those barriers. Many of the barriers that we perceive now as limiting will be surpassed as well. So I have a lot of confidence in the creativeness of this industry to keep refreshing itself. The problems are getting more and more difficult. As a result, the idea of finding replacements has come to the forefront of very serious discussions.

From the university side, it is particularly clear that funding from government as well as from industry consortia is really pushing the university researchers to find a replacement for CMOS. I’m a little concerned that that allocation of research resources, both money and talents of the nation, is not the best budgeting of our R&D resource. That is why I want to advocate that rejuvenating CMOS is perhaps a better battle cry that will lead to greater benefit to the industry than an overly emphasized idea of replacing CMOS. It is a balance that I’m advocating.

MICRO: Can you provide examples of some of these types of, if you will, nano-CMOS-type rejuvenating technologies?

HU: It’s very important to find ways to reduce the power dissipation, and that can be done through improvement in the materials. In particular, we really want a thin-film material that we can put on top of a silicon substrate that has higher carrier mobilities, so that we don’t need as high a voltage to drive large currents through the transistors to keep the speed of the circuit up and, at the same time, allow us to use lower and lower power-supply voltage. That would be a very desirable goal. And that is in the category of rejuvenation as opposed to replacement.

The idea of strained silicon—there is still a lot of juice that can be squeezed out of that. After that, some new material such as germanium can be considered. Thinking more grandiosely, one can even take on a project to design a man-made semiconductor material—something that we cannot find from the handbook of physics or chemistry or materials.

Another example would be looking for a new device concept that will beat the fixed rate of turnoff. The experts call this a “60-millivolt-per-decade tyrant.” That term means the minimum threshold voltage that a transistor must have, so if we can beat that limit, we can reduce the power-supply voltage and also reduce power dissipation.

MICRO: What about in the area of the advanced memory technologies, such as MRAM, NRAM, maybe big NVM-type structure, FinFETs, things like those? What do you see as their potential in terms of being rejuvenators?

HU: There’s a lot of research under the umbrella of nanotechnology. What’s special about this effort is that there are many chemists, physicists, and materials scientists involved in nanotechnology research relative to the semiconductor technology research that our industry has been used to. And that nanotechnology research effort opens up a lot of opportunities to create materials with unusual properties. These materials will open up new doors for memory, in particular nonvolatile memory.

Nonvolatile memory is interesting, because the world really wants a…very large memory capacity for archival storage. We not only want to store documents and music and now images, we will want to store videos. Basically we want to store an entire lifetime experience. So the market is there. Another good thing about nonvolatile storage is that it doesn’t take much power. It does take power to write, but it does not take much power to read. It certainly does not take any power to keep the data stored.

Finally, nanotechnology research will give us new opportunities, new materials, new mechanisms to store information in these nanoengineered materials. So when you put all this together, I think memory is probably the area where we’ll see the greatest number of innovations and the greatest growth in the semiconductor industry. It will be a wonderful direction for people to look for rejuvenation.

MICRO: Let’s talk about one particular type of emerging technology, and that is carbon nanotubes. How do you see CNTs fitting into this vision of a rejuvenated CMOS?

HU: In my thinking, CNT can be a good candidate for rejuvenating CMOS. The point is that we should be looking for ways to use CNT in a manner that’s compatible with the manufacturing infrastructure of integrated circuits and produce transistors that have the characteristics that integrated circuits require—namely large drive current, at least three terminals, etc. CNT has demonstrated a potential to do exactly those two things. That is, its manufacturing techniques can be compatible potentially, and it can produce transistor behaviors that are very similar to the transistors that the integrated circuit community has come to expect. As a result, I think the carbon nanotube is a good candidate. Fortunately there are very capable researchers in the CNT area that have taken on the challenge of making CNT a manufacturable technology in the IC manufacturing environment. So with time, I think CNT may turn out to be a formidable competitor with the semiconductor materials that we talked about earlier.

MICRO: What would you see as some of the key challenges facing the evolution of CNTs from the research phase or pilot stage into a more mainstream production environment?

HU: I think there are two things that are standing in the way and must be overcome. One is to be able to lay the CNT down on a silicon substrate in a prescribed direction, uniformity, and geometrical arrangement. The second is that we have to have good control of the CNT’s characteristics—namely whether it is semiconducting or metallic, and the diameter of the CNT, which determines the band-gap energy and some other characteristics. So laying out the CNT in a controllable manner and making the CNT with controllable characteristics, these are the two things that must be done.

CNTs, right now, are grown in a haphazard manner. They are kind of like weeds. Somehow we have to make them lay out like carpet wherever we want them to go rather than growing like weeds. The other thing, it turns out, is that some CNTs are semiconducting and some are metallic. The metallic ones cannot be turned off by a gate, so they become a leakage path. Those are examples of the properties we have to control.

But given the rate of the progress of CNT research recently, I am actually more optimistic than many people about the possibility that the CNT will turn out to be a breakthrough material for integrated circuits. But there are other competitors of course.

MICRO: Yeah, one thing that many people talk about relates to your second point. And it actually has to do with the supply chain. With the infrastructure that you need to have suppliers—it may start out like the old days, when the chip companies did a lot of their own tooling and materials. But eventually, you need to have companies that can provide spec’ed CNTs at the right purity and the right performance characteristics, which they can create by the many trillions, when we’re talking about CNTs. Much like wafer makers have really improved the quality of the wafers that they offer.

HU: You’re absolutely right. And it usually goes in the sequence. Some research laboratories, and very often, especially in this case, probably some university laboratories, will find some clever ideas that show, hey, it can be done. If you did this, then these things can be put down in a very controllable manner. After “the feasibility” of doing the controllability is demonstrated, then some corporation will make the necessary much bigger investment to develop the machine to do that.

We are still at this first stage. If there is a breakthrough in the first stage, the progress of the second stage actually is more predictable. As long as the market is there, some equipment companies will be able to take a breakthrough in the research lab and turn it into turnkey equipment.

The investment in carbon nanotubes as a material for CMOS is a worthwhile one, and I would lump that into a rejuvenation option, although many people consider CNTs as the young CMOS. So there may be some difference in the communication there. To me, what CMOS really means is things that are compatible with this very huge manufacturing infrastructure as well as this huge circuit and product infrastructure. So things that can fit into those two infrastructures are great candidates for rejuvenating CMOS.

MICRO: There’s another emerging technology—FinFET. Why do you see that as a promising rejuvenator?

HU: FinFET or other new structures similar to it is a good rejuvenating technology. It is something that will take a little bit more work than before, but it’s not a lot of work and uses the manufacturing infrastructure and the design infrastructure that the industry is good at.
What this structure does is that it allows us to turn off the transistor much better than the transistor that’s used today. Therefore, we will be able to continue to shrink the transistor by maybe 10 times more in linear dimensions or 100 times in area. That’s why it is attractive. Any time we make a change, there are a lot of other supporting changes that have to be made, like the design software tools, even the circuit libraries and circuit IPs. They all have to be redesigned, and that takes time.

Memory, on the other hand, might be able to benefit from infrastructure earlier, because memory design is more straightforward. One can afford to spend a lot of time optimizing a memory cell. This comment applies to SRAMs as well as DRAMs and the nonvolatile memories. So it’s probable that we will see FinFET. In fact, I believe FinFET will be applied first to a variety of memories. That will give the designers comfort to adopt it as a general replacement for the planar CMOS transistor.

MICRO: A lot of what we’ve been talking about is transistor-related solutions—front end of line, if you will. What about on the interconnect side? What are some of the innovations that you could see there that will help extend CMOS’s life?

HU: The visions in the back end are fewer than in the front [end] direction of structures and materials, and that is a concern. I hope that situation will change, that there will be more new ideas. But the fact is that it has proven to be a very difficult challenge. Many of the attempts to develop optical interconnect or even RF interconnect have not progressed as fast as the industry would have hoped. And low-k will of course continue to improve and progress. But the latest international technology roadmap actually slowed down the projection of low-k’s improvement compared with previous years’ projections. This is unusual and therefore highly significant. It just reflects frustration that the back-end technologies have not benefited as much from new, innovative solutions. I believe it’s not for lack of trying, but because the problem is just very difficult.

So what can we do about that? On the one hand, we cannot give up and should continue to look for an innovative solution. On the other hand, we should communicate this fact very honestly to the design community and expect the design community to share a bigger portion of the burden of dealing with the back end. I think the back-end problem basically has to do with what is sometimes called noise, sometimes called crosstalk; second is the delay; third is the power due to the long interconnect. All of these three things do have design solutions. It has always been a question of what will be cheaper.

Would it be cheaper to solve this from the material and manufacturing technology side? Or would it be cheaper to solve this problem from the design and architecture side? I think open communication between back-end manufacturing and the design community is going to be the key for orderly progress of CMOS technology development.

MICRO: One sort of innovation that I wanted you to talk about, is the idea of a three-dimensional interconnect. Obviously, something with 10 levels of metal in it is already somewhat three-dimensional. But what about the kinds of stacking ideas that people are pursuing in terms of putting the interconnect into a more vertical direction?

HU: I think 3-D integration makes a lot of sense for memory, because adding an additional layer of some simple memory does not even require high-quality transistors—and, by the way, there are examples of that. Matrix Semiconductor makes three-dimensional memory. If we can add layer upon layer of simple structures, that seems to make sense.

Another reason why memory makes sense is that it tends not to draw much power, especially the nonvolatile memories. We can add layer upon layer, each layer should not consume a lot of power, and each layer should not require a lot of processing steps. This means that adding complex logic microprocessors in a three-dimensional manner will have to face a lot of difficulties and challenges. Nothing is impossible in this industry. But it is good to keep the relative difficulties and rewards in perspective. At this point, memory is the area that will benefit most from three-dimensional integration.

MICRO: It seems like one of the themes of our conversation is that the memory side is the one that seems to have more potential for rejuvenation in some respects than the logic side.

HU: Yes, I agree with you. There are more opportunities there. But I would say that the logic side can keep going along this rejuvenation path for many decades to come.


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