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Adopting CMP processes to achieve new materials integration

Robert L. Rhoades, Entrepix; and Jim Murphy, Fairchild Semiconductor

Over the past decade, the general attitude toward chemical-mechanical polishing (CMP) has evolved. Once reluctantly accepted as a niche planarization process for only the most advanced devices, it has come to be embraced as a mainstream process for high-volume CMOS manufacturing across multiple technology generations. In fact, CMP is recognized as a critical enabling process for 0.35-µm devices and below. In addition, as the process has become better characterized and understood, it is increasingly being used to address many of the more complex integration and yield issues encountered in a wide range of device designs.

This article examines the development of CMP processes for potential use with three combinations of materials for advanced semiconductor devices. In each case, the top layer of material was deposited over the patterned features in the second material, which also served as a stopping layer for the CMP process. After polishing, the surface of the wafers was supposed to be planar and smooth, and both materials were supposed to be exposed in their respective regions. When implemented properly, this approach has great appeal, because the presence of the stop layer enables the polishing process to have a wide overpolish margin while still leading to nearly the same output result.

The material combinations investigated here included borophosphosilicate glass (BPSG) over patterned silicon nitride, polysilicon over patterned oxide, and chemical vapor deposition (CVD) oxide over patterned silicon features. Process results ranging from good to excellent for each of these combinations are presented, along with example cross sections of test structures.

Polishing Single- versus Mixed-Material Systems

Polishing processes can be grouped into two general categories: single-material and mixed-material systems. Examples of single-material processes include polishing of silicon wafers or other bulk materials, interlevel dielectric planarization, and any process in which only one type of material is exposed during polishing. Because of the mechanical or chemical properties of the material being polished or tight process specifications, these processes can be complex. However, they are generally more straightforward than mixed-material applications.

Examples of mixed-material applications in a CMOS fabrication flow include tungsten plug CMP, shallow-trench isolation (STI), and copper dual-damascene processing used for advanced interconnects. With mixed materials, the process not only must be compatible with each material individually but also must have the proper ratio of polishing rates once all materials are exposed. The ratio of these relative polishing rates, or selectivity, is expressed as a reduced ratio and is usually characterized by polishing blanket films of each material separately using the same pad, slurry, and process settings. The polished surfaces of these blanket-film wafers can provide great insight into wafer surface properties, defect levels, and other process factors.

As informative as independent blanket-film results can be, process characterization is incomplete until data are obtained from patterned wafers that contain all the materials used in the process. In this study, complete process characterization was achieved by processing test wafers that had a broad range of feature sizes and materials that were deposited in uniform films.

Experimental Approach

For each combination of materials discussed in this article, a similar experimental approach was used to characterize polishing behavior. This approach had the following process flow:

• Blanket-film and patterned test wafers were processed.

• A few blanket-film wafers were test-polished using potential pad, slurry, and process settings.

• Results were compared for removal rate, removal uniformity, and selectivity to the stop layer.

• The pad, slurry, and process were selected to achieve the best expected balance of process metrics.

• First-pass optimization of the blanket-film process was performed.

• The decision was made whether to proceed or not to proceed to patterned-wafer processing.

• The process was modified to achieve the desired topographical performance over varying structures.

• Patterned wafers were polished and the surface properties were characterized.

• Scanning electron microscope (SEM) cross sections were generated.

Silicon dioxide can be deposited or grown on silicon wafers using a variety of processing methods. Because these methods lead to subtle differences in film stress, density, and other metrics, they have different names.

Nevertheless, they are actually variations of the same basic process. The experiment discussed in this article included several variations of the same basic material and process: tetraethylorthosilicate (TEOS), thermal oxide (or simply oxide), and subatmospheric chemical vapor deposition (SACVD).

Polishing Boron- and Phosphorus-Doped TEOS Oxide (BPTEOS) on a Silicon Nitride Stop Layer. The first material system tested consisted of a top layer of BPTEOS and a bottom layer of silicon nitride. Initial screening tests involved polishing blanket-film wafers using several pads and slurries across a range of process settings. The pads used included IC1000 (without subpads) from Rohm & Haas Electronic Materials (Phoenix), while the slurries used included Microplanar STI 2100C from DA NanoMaterials (Tempe, AZ). The first-pass optimized results of these blanket-film polishing runs are presented in Table I.

Table I: Process inputs and results for BPTEOS on silicon nitride.

The patterned test wafers for this mixed-material system had test structures of various sizes etched into a silicon wafer that was then coated with a uniform layer of silicon nitride followed by a uniform layer of BPTEOS oxide. The processing goal was to remove the BPTEOS oxide over the field areas, stop on the nitride layer, and planarize the inlaid BPTEOS in the recessed features. A typical feature is shown in Figure 1.

Figure 1: SEM image of a test structure with planarized BPSG over silicon nitride features. The nitride stop layer is still visible over the topography.

As seen in the cross section, the planarization of the BPTEOS across inlaid features was excellent. Inspection of numerous sites across the wafer also indicated that the selectivity of the CMP process was adequate to stop on the nitride layer without breaking through—even across a wide range of feature sizes and spacings up to 2.5 µm. Patterned wafers were subjected to various amounts of overpolish to test the robustness of the nitride stop layer. The micrograph in Figure 1 is typical of a wafer with 8% overpolish. Wafers that were subjected to as much as 16% overpolish still displayed ample nitride thickness, with no signs of breaking through in the narrow field areas.

Polishing Polysilicon on an Oxide Stop Layer. The second mixed-material system tested consisted of a top layer of polysilicon and bottom layer of silicon dioxide. Polysilicon is frequently used to fabricate semiconductor devices, especially low-current, moderate-voltage connections such as gate electrodes. However, most polysilicon processing has traditionally been performed using standard deposition, photolithography, and etching techniques. This portion of the experiment investigated the possibility of polishing polysilicon to achieve a sufficient level of planarity and a surface quality that is suitable for future damascene applications.

In general, polysilicon is difficult to polish in a tightly controlled fashion because slurry choices are limited. Using most standard oxide slurries, the poly polishing rate is uncontrollably high, and the resulting surface is generally rough or pitted. Most prime silicon slurries create an unacceptable level of roughness on poly because of differential polishing rates based on the film’s grain orientation. However, at least one commercial slurry, Ultrasol S10 from Eminess (Tempe, AZ), has been developed specifically to polish polysilicon. The results of using this slurry are presented in Table II. The dual pad stack used in this test was the IC1000/Suba IV from Rohm & Haas Electronic Materials.

Table II: Process inputs and results for polysilicon on silicon dioxide.

For most device applications, a uniform film of polysilicon is deposited and then patterned using photolithography and etch processes to create the desired features. Alternatively, polysilicon features can be created by etching the desired pattern into an oxide layer, depositing a uniform film of poly-silicon thick enough to fill the pattern and generate over-fill above the desired final surface, and polishing back to the oxide surface while leaving polysilicon in the recessed features.

As seen in the micrograph in Figure 2, the polishing process successfully stopped at the oxide layer between the features and planarized the polysilicon across the features. The CMP process performed on this wafer included more than 25% overpolish. Other wafers that received as much as 40% overpolish showed no signs of breaking through the oxide at the corners or in the narrow field spaces.

Figure 2: SEM cross section image of a patterned test structure for the poly CMP process on a silicon dioxide stop layer. (An additional oxide capping layer was deposited during SEM sample preparation.)

Polishing SACVD Oxide on a Silicon Stop Layer. The third and final mixed-material system consisted of a top layer of SACVD oxide with a single-crystal silicon stop layer. This combination of materials was especially difficult to work with because of the poor selectivity of most oxide CMP slurries to single-crystal silicon. In general, the process resulted in inverse selectivity—in other words, the polishing rate on the silicon was approximately three times faster than that on the oxide. That result was exactly the opposite of the desired behavior for polishing processes.

Fortunately, some STI slurries exhibit a degree of selectivity to silicon when optimized for this parameter. After screening determined that the differences among these slurries are relatively small, the decision was made to use the same slurry that was used in the BPTEOS-on-silicon nitride test. Again, an IC1000/Suba IV pad stack was used. The results of this test are presented in Table III.

Table III: Process inputs and results for SACVD oxide on silicon.

The patterned test wafers used in this portion of the experiment had features of various sizes etched into a silicon wafer that was then coated with a uniform layer of SACVD oxide. Since the silicon itself was the intended stop layer, micrographs simply showed a single interface in the buried feature rather than a layer of material separating a filled feature from the substrate.

As shown in Figure 3, the tops of the polished features were extremely planar, and the general effect of creating inlaid oxide features on the silicon surface was achieved. However, as can be inferred from the blanket film data, this process exhibited a fairly low degree of selectivity between the SACVD oxide and the underlying silicon. Hence, the overpolish margins on patterned wafers were smaller than those observed on processes with higher selectivity. Indeed, this result was confirmed on wafers polished for different lengths of time. Preferential corner erosion was seen on structures with larger spaces, as shown in Figure 4. Trade-offs between process margins and design sensitivities would have to be closely evaluated if this particular process were to be considered for a potential device flow.

Figure 3: SEM image of a test structure with planarized SACVD oxide filling patterned features in a silicon wafer. (The surface was coated with another layer of material after CMP for SEM sample preparation.)
Figure 4: SEM image of a test structure with larger openings. Preferential corner erosion was seen on some structures near larger open areas.


All three mixed-material systems discussed in this article exhibited reasonable polishing behavior and were potentially viable candidates for further development, although the third system would require more developmental work than the first two. Both blanket-film results and patterned test wafer results indicated that the concept of using a selective CMP process to create inlaid structures in mixed-material systems is worthy of further investigation. Overpolish margins were particularly good for BPTEOS on a silicon nitride stop layer and polysilicon on an oxide stop layer.

Robert L. Rhoades, PhD, is the chief technology officer at Entrepix in Tempe, AZ. He has held engineering and technology management positions in the semiconductor industry for more than 21 years, the last 12 of which he has focused on CMP. The author of more than 50 technical publications and conference presentations, he received a PhD in electrical engineering from the University of Illinois in Urbana-Champaign. (Rhoades can be reached at

Jim Murphy is an engineering section manager at Fairchild Semiconductor in West Jordan, UT. He has played an engineering role in the semiconductor industry for more than 23 years, primarily in the areas of thin films, metallization, and CMP. He received a BS in medical technology from South Dakota State University in Brookings. (Murphy can be reached at

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