Advertiser and

Buyer's Guide
Buyers Guide

Chip Shots blog

Greatest Hits of 2005
Greatest Hits of 2005

Featured Series
Featured Series

Web Sightings

Media Kit

Comments? Suggestions? Send us your feedback.


‘Rapid learning’ keys TI’s ramp

Texas Instruments’ Venu Menon revealed intriguing details about his company’s ramp to 65-nm technology and the challenges facing it at 45 nm and beyond during his keynote at the Advanced Semiconductor Manufacturing Conference in Boston. One part of TI’s recipe for ramp success is its “rapid learning cycle” program, which he said can handle a six-level-metal wafer lot at 0.6 to 0.8 days per mask level. This translates into a two- or threefold improvement in the yield learning cycle rate.

Menon also discussed transistor performance, interconnect, design for manufacturability, and other aspects of the company’s process and device technologies. On the transistor front, he described how TI used a combination of gate length and gate oxide scaling, including strain techniques and the introduction of new materials, to achieve some performance enhancements, but needed changes in device architecture to get the complete performance pop they were looking for.

Interconnect at 65 nm, Menon said, accounts for at least 50% of delay problems in typical dense logic chips. When k-value doesn’t scale, “a big knob in your performance toolbox has been taken away.” Since the introduction of low-k dielectric materials has been slow, with k-values still in the 2.7 to 2.9 range, he encouraged suppliers to work on bringing down the k-values of adjacent materials such as etch stops to help lower the effective k-value through the whole stack.

Menon also talked about how design innovations have been or should be used to compensate for process scaling limitations. He stressed that designers need to have tools that can help them compensate for process variations and manufacturability issues in their designs. Variations range from etch effects and CMP selective process biases to within-die and die-to-die data to the more difficult to model lot-to-lot and fab-to-fab data. He cited another opportunity for the supplier base, saying there’s a critical need for tools to help designers better understand manufacturing variations. —TC  

Companies score funding

Three up-and-coming companies have secured investment and credit-line funding. Syntricity received a credit facility of $1.5 million from GE Commercial Finance’s technology lending unit, to go along with the $5.8 million it scored in Series B funding led by Windward Ventures in late 2005. The San Diego–based enterprise yield management software company will use the line to help manage its rapid growth and support increased demand for its software-as-a-service model.

Atom-probe tomography company Imago Scientific Instruments completed a $3.4 million round of equity funding led by Draper Fisher Jurvetson, Portage Venture Partners, and Cipio Partners. The investment comes on the heels of Imago’s purchase of Oxford NanoScience from Polaron.

Qcept Technologies closed a follow-on Series B financing round led by Siemens Venture Capital. The Atlanta-based nonvisual residue wafer inspection system developer will use the monies to accelerate product development, sales and marketing, and brand awareness.

Princeton wins USDC award

The U.S. Display Consortium has awarded $1.7 million to the Princeton Institute for the Science and Technology of Materials for a two-year program targeting the development of flexible backplanes. The R&D contract will help the university develop the process technology and expertise to produce amorphous silicon thin-film transistors (TFTs) on a high-temperature-capable polymer substrate. One gating factor in making TFTs on polymers is the processing temperature limit, so the Princeton work is based on a new clear, flexible polymer foil substrate that can withstand the heat of “glasslike” processing. Program milestones include demonstrating an electrophoretic test array and an organic light-emitting diode (OLED) test array on the plastic substrate by the end of the first year.

CMP consumables top $1B

A new industry analysis says the CMP consumables market rose to a record $1.1 billion in 2005. Linx Consulting’s “CMP Technologies and Markets to the 45 nm Node” reports that the global market for slurries and pads last year was a combined $975 million, with cleaners and conditioners pushing the sector over the billion-dollar mark. The firm sees the number of CMP operations increasing at about a 15% compound annual growth rate over the next four years, with the consumables market reaching nearly $1.8 billion in 2009.

Rohm and Haas Electronic Materials continues to dominate the pad segment, garnering 41% of the overall consumables market, while Cabot Microelectronics leads the slurry manufacturers in all but one major product category and holds 28% share overall. Other major players in the overall consumables market include Hitachi (8%) and Fujimi (6%), with JSR, DA Nanomaterials, Planar Solutions, Cheil, Thomas West, and others accounting for the remaining 17%. The report breaks down the percentage of the total number of polishes by device type in 2005, with logic still way out front with 82%, followed by DRAM at 13% and flash at 5%.

The document also features forecasts for CMP operations by device type and application; detailed perspectives on CMP operations for 90-, 65-, and 45-nm process technologies; emerging technologies; and analysis of supplier positioning, including the impact of new players.

MicroHome | Search | Current Issue | MicroArchives
Buyers Guide | Media Kit

Questions/comments about MICRO Magazine? E-mail us at

© 2007 Tom Cheyney
All rights reserved.