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SIA ROADMAP UPDATE

New definition, advanced defect detection tools are keys to highway

Chipmakers will require detection, inspection, and review technologies with particle sensitivities between 0.18 and 0.10 µm at greater throughputs than are currently available, according to the team heading up the defect reduction technology crosscut working group. The coordinating body also emphasizes that the tools will need some degree of artificial intelligence, such as automated defect classification and factory-integrated data management. Developing these capabilities will bring the industry closer to the total-system solution required for next-generation defect detection and prevention.

Based on a cursory review of the earlier roadmaps, this assertion is one of three "key messages" discussed in a draft of the 1997 revision, which is once again being prepared by the Semiconductor Industry Association (SIA). First published in 1992 and revised in 1994, the SIA document focuses on the technologies required to manufacture successive generations of semiconductors to 2010. The roadmap describes requirements for producing ICs as linewidths shrink from 0.35 to 0.07 µm. The new revision is scheduled for publication in November 1997.

The two other key points emphasized by the working group are:

• Contamination control will be required within equipment in order to attain the defect densities needed for 90% yield. Detection of particulate and nonparticulate contaminants in the process environment will enable process engineers to better understand developments in such crucial areas as in situ chamber cleaning. Better modeling of contamination formation, transport, and deposition will also be needed to help engineers reduce tool-related defects.

• Purity requirements for gases, liquid chemicals, and UHP water will be relaxed. At current purity levels, these process-critical materials are now understood to contribute very little to particulate contamination that can limit yield. Trace ionic contaminants within certain chemicals are adequate for meeting the requirements of 0.25-µm processes.

CFM is too restrictive a term, asserts Wolleson. One of the main reasons for forming the crosscut technology working group is "to take advantage of the synergy" created by the establishment last year of the NSF/SRC Research Center on Environmentally Benign Semiconductor Manufacturing, he says. Housed at the University of Arizona, the center combines the efforts of faculty and students at Arizona, Stanford, UC Berkeley, and MIT.

"What we're trying to do is combine the agendas of defect reduction, contamination reduction, and environmentally benign [manufacturing]," Wolleson explains. "It's really easy to take that agenda and make it confrontational and controversial and counterproductive, but we want to take it seriously. There's a lot of parallelism."

The crosscut group "has stakeholders in all the technology working groups [involved in writing the revision], such as ES&H, factory integration, metrology, and defect reduction technology," points out David Jensen, a group member and a senior process engineer in contamination-free manufacturing for Advanced Micro Devices in Austin, TX. Others involved in the effort are representatives from SRC, Sematech, academia, and national laboratories such as Sandia. In addition to this core membership, the group contains representatives from seven chipmakers and "a number of other folks from companies like Ashland Chemical, Air Products and Chemicals, Tencor Instruments, KLA Instruments, and Applied Materials."

At the suggestion of cochair Dinesh Mehta, SRC's director of interdisciplinary research programs and strategic initiatives, the preliminary document contains a broader definition of yield learning and defect reduction technology than previous versions. Under the defect detection rubric the roadmap will address four main subtopics: yield model and defect budget; defect sources and mechanisms; defect detection; and defect prevention and elimination. The following points summarize the working group's proposals for each of the four areas and the scope of responsibility for each defect reduction subgroup:

• The yield model and defect budget subgroup sets overall defectivity targets for microprocessors, DRAMs, and ASICs based on corresponding yield targets. Says Jensen: "This [focus] is intended to utilize yield modeling in order to develop tool targets and process-induced defect budgets for each layer and each tool in the factory for each technology node." The characterized data arising from new techniques of wafer-map analysis can produce information with the potential to offer yield model inputs that can help engineers improve real-time yield monitoring and prediction. Tool developers and suppliers are the targeted users.

• Defect sources and mechanisms "are a little bit new for the contamination control discipline," notes Jensen. "We want to have better methodologies and tools to be able to identify root causes of defects—how they're transported, for example—and eventually have real-time feedback to the process for critical operations and control of tools." Fault-isolation techniques and modeling to isolate tool and process sources of defects come into play. "This is kind of an interesting area," Jensen says. "I think we need to do more research and development in these kinds of things."

• The defection detection subgroup "is pretty much your traditional defect detection activity," Jensen explains. The future technology requirements for the detection, classification, and review of process-induced defects fall under this heading. Defects related to the qualification of process tools, issues involving silicon and similar materials, and defects made during wafer processing are also included. Defining key characteristics of patterned and unpatterned detection tools, in situ particle monitors, and in-line defect review equipment is another important aspect. "In the roadmap you'd see the technology needed for imaging systems and light-scattering systems—the KLAs, the Inspex tools, and the like," Jensen says.

• The final subtopic, defect prevention and elimination, defines itself. "It's the traditional [approach of], 'OK, we've got a bunch of defects, how do we get rid of them?' " Jensen points out. The focus here is on the cleanliness of such parameters as the processes and the air. The subgroup re-lies on the output of the yield analysis group to define the permitted defect budget for each tool and relies on the defect sources section for a fundamental understanding of defect sources. Technology needs are segmented into two categories, accord-ing to the draft document. They are process-induced defects caused by gases, liquids, and DI water; and defects caused during wafer transport, storage, and handling in the cleanroom.

"The agenda of reducing the number of defects in situ in the machine is a very important one," emphasizes Wolleson. "You get a certain defect count in manufacturing today. The big question is, where do defects come from? It's a search-and-destroy operation. If you don't find them you can't kill them."

The operation requires a combination of statistical and analytical weapons, he says. The technology director notes that AMD's Submicron Development Center in Sunnyvale "is probably one of the cleanest fabs on Earth, and my quip is that the insides of the machines [there] have more contamination than the outside." Wolleson cites a war story as an example of the problem. A few years ago AMD engineers discovered tungsten particles on processed wafers. Some detective work revealed that the contamination "was precipitating out" from the photoresist. "You don't get that answer from just doing particle counting with a KLA or an Inspex tool—although those are vital tools. Once you discover the contaminants it's not the end of the mystery, it's just the beginning of it.

"It's not a horror story or a career-ending problem," Wolleson jokes, "but if you're going to compete you've got to get your yield up. There are probably dozens of those vignettes."

The revision is on schedule, he says. "We actually started a little sooner on this one than we did on the last one, and in general we're probably a little more coordinated at this point than we were three years ago." A surprised Wolleson notes that the response to the two previous volumes "has really been amazing." When the 1992 edition appeared SIA printed 4000 copies of the executive version and 1000 copies of the full book. The earlier edition "shipped 13,000 copies. The '94 version went zinging through 13,000 copies in a couple of months.

"We hope this will be a better book," Wolleson quips. "We believe in continuous improvement."

(A roadmap workshop is scheduled for May 27­29 at the University of Texas, Austin. Anyone interested in participat-ing in the overall workshop or in the activities of the defect reduction group may telephone David Jensen at 512/602-6730 or Dinesh Mehta at 919/941-9435.)

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