TECHNICAL PROGRAMS

The following is a partial list of courses, workshops, forums, and symposia taking place during the San Francisco segment of Semicon West this year. All programs will take place at the San Francisco Marriott unless otherwise noted.

SUNDAY, JULY 13

Program Cochairs: James McAndrew, Air Liquide, and Cliff Fields, Intel

A Comparative Study of Corrosion-Resistant Alloys for Use in Distribution Systems
Howard Mastropiero, Evan Hinshaw, and Juan Alvarez, MKS Instruments

Modular Gas System Solutions
William Culwell, Insync

All Vapor Phase Delivery of Electronic Specialty Gases
Hwa-Chi Wang, Richard Udischas, and Benjamin Jurcik, Air Liquide

Analysis of Cost vs. Benefits for Integrated Gas Delivery Systems
Sowmya Krishnan, Ultra Clean Technology

Pressure Transducers for UHP Gas Distribution Systems
Richard Rosenblum, Ametek

Alternative Gas Distribution System Impurity Analysis Using Remote Sampling and Analysis Techniques
Jeffrey L. Breisacher, SAES

The Effect of Stainless-Steel Melt Methods on the Corrosion of Weldments in UHP Gas Lines
Craig Burton, Valex

Panel Discussion: William Locke, Cambridge Fluid Systems; Angel Martinez, Integrated Design Systems; and others

Workshop on Contamination in Liquid Chemical Distribution Systems
1–5 p.m.

Program Chair: Tom Talasek, General Chemical

Opening Remarks: Tom Talasek, General Chemical

Measurement of Ultra-Low Levels of Total Oxidizable Carbon (TOC) in Water for Semiconductor Manufacturing
Steven Stiller, Anatel

On-Line Detailed Wet Chemistry Bath Analysis Provides Bulk Chemical Distribution Systems with the Information to Maximize Bath Performance and Life
Peter Robertson, FPM

Specification and Verification of Metallic Extractables in Fluid Handling Components
Donald C. Grant, CT Associates

Accelerated Qualification of Chemical Distribution Systems for New Fab Startup
Jennifer Sees, Texas Instruments

Reduction of BOE Bath Startup Times through Utilization of Hydrophilic Membrane Filter Media
Mark Nicholas, PTI Technologies

Purge and Commissioning Procedures for Bulk Liquid Delivery Systems
Robert Zurich, Schumacher

Filtration of CMP Slurries inChemical Delivery Systems
Zhenwu Lin, Millipore

Parameters for Monitoring CMP Slurry Stability and Contamination
Travis Lemke, FSI International

Panel Discussion

Plasma Etch 97—Backgrounder and New Developments
1–5 p.m.

Instructor: Daniel L. Flamm, University of California, Berkeley

Welcome and Introduction
Daniel L. Flamm

Plasma Etching Fundamentals and Emerging Trends
Daniel L. Flamm, University of California, Berkeley

Plasma Etch Challenges for Deep Submicron CMOS Processing
Calvin Gabriel, VLSI Technology

New Metrics and Techniques for Plasma Damage Control
James P. McVittie, Center for Integrated Systems, Stanford University

Environmental Impacts, Feed Gas Chemistries, and Effects of Gas Impurities in Etching Processes
David S. Green, National Institute of Standards and Technology (NIST)

Final Questions/Answers/Discussion

STEP: Equipment Reliability & Productivity
1–5 p.m.

The agenda includes: description/status of SEMI E10; real-world implementation experience: E10 and TPM/OEE; key metrics--MTBF, MTTR, uptime, availability, and overall equipment effectiveness (OEE); issues with TPM, capital productivity problems; discussion/demonstration of computer-based training for E10 users; overview and status of automated E10 data collection (ARAMS)—SEMI E58.

MONDAY, JULY 14

The SEMI Enabling Products and Services Section (EPSS) is a SEMI-sponsored special interest group for SEMI members who supply products and services to the semiconductor industry which enable the development and manufacturing of semiconductor devices. The group is concentrating on a program that generates information and provides insight on how suppliers can more effectively communicate and interface with their chipmaker customers.

300-mm Wafer Standards Workshop
8 a.m.–noon

Presented by the 300-mm Diameter Wafer Specification Task Force
Chaired by Howard Huff, Herman Fusstetter, and Masaaki Yamamichi, Silicon Wafer Committee

This workshop, seventh in a series of workshops on 300-mm silicon wafer specifications, will focus on development of prime wafer specifications for wafer dimensions and other critical properties.

Silicon-on-Insulator (SOI) Processing Technology
8 a.m.–12:30 p.m.

Program Cochairs: Sookap Hahn, Pacrim Technology, and Tohru Hara, Hosei University

Strategic Directions and Challenges for CMOS Manufacturing on Silicon-on-Insulator (SOI) Substrates: Materials, Device and Process Integration Issues for 0.18 Micron and Beyond
P. K. Vasudev, Sematech

Market Acceptance of SOI Materials
Robert A. Craven, SiBond

200-mm SOI Wafers Using the Smart Cut Technology
A. J. Auberton-Herve, SOITEC S.A.

New SOI Epi Wafer—ELTRAN
Takao Yonchara, Canon

Developments in SIMOX-SOI Materials and Manufacturing
Michael Alles, Ibis Technology

Applications of Bonded SOI to Ultra-High-Speed BICMOS LSIs
Takahide Ikeda, Hitachi

Recent Advances on SIMOX CMOS Process Technology for High-Speed/Low-Power Circuits
Keizo Sakiyama, Sharp

Fully Depleted CMOS/SIMOX Technology for Low-Power, High-Speed ULSIs
Toshiaki Tsuchiya, NTT

Symposium on Deep UV Lithography for Process Engineers
8 a.m.–5 p.m.

Program Chair: P. Rai-Choudhury, SPIE—International Society for Optical Engineering

Deep UV Lithography Equipment
Harry Levinson, Advanced Micro Devices

Resist Processing Technology for Deep UV Lithography
John Petersen, Sematech

Metrology for the Deep UV Era
Joe Griffiths, Lucent Technologies

Deep UV Lithography: Future Trends
Roderick R. Kunz, MIT–Lincoln Laboratory

Mask Technology at the Center of Advanced Lithography
Lars Liebman, IBM Microelectronics

SEMI Chemical and Gas Manufacturers Group Meeting
10:45 a.m.–12:15 p.m.

The SEMI Chemical and Gas Manufacturers Group (CGMG) is a SEMI-sponsored special interest group for SEMI members who supply chemicals, gases, and related products to the semiconductor industry. The group is in the process of implementing a program to generate and disseminate special market statistics for chemicals and gases among those companies who are willing to participate in this group.

Cost of Corrosion Standards Workshop
1–3 p.m.

Presented by the Gas Panel Test Methods Task Force
Chaired by Steve Lau (Corrosion Task Force Leader), Semi-Gas Systems

This workshop will focus on the impact of corrosion on semiconductor device fabrication processes. These costs include equipment downtime, replacement cost of equipment, and potential device yield reduction caused by process contamination. Contamination can occur throughout the gas distribution delivery system. The gas delivery system, gas regulators and controls, process gas piping, and components can contribute to contamination. Each of these items could cause corrosion and therefore have a negative impact on the cost of device manufacturing.

Gas Purification Cost of Ownership (COO) Standards Workshop
3–5 p.m.

Presented by the Gas Purifiers Task Force
Chaired by Mary Lou Markowski (Gas Purifiers Task Force Leader), Praxair

This workshop will describe and determine the value of COO models used for gas purification capital equipment. Cost is a significant factor in any COO model, as is system reliability and uptime. Gas purifiers can prevent unscheduled downtime, reduce maintenance downtime, and improve process control leading to cost reduction by as much as 20% in gas distribution systems. The amount of gas purification needed to maintain and increase the reliability of gas distribution systems is one piece of the "good system design" puzzle that includes maintenance, gas purity, material and component selection, and older process equipment.

Facility Layout Design in the Semiconductor Industry—Will Your Equipment Be Ready?
1–5 p.m.

Instructors: Jose Padillo and Doron Meyersdorf, Tefen

Course outline: Facility performance parameters, macro and micro layout, layout alternatives, generating layout alternatives, evaluating layout alternatives, case studies, and future fabs—will your equipment be ready?

Symposium on Lithography at an Inflection Point
1–5 p.m.

Program Chair: Paul P. Castrucci, Paul Castrucci and Associates

Introduction
Paul P. Castrucci, Paul Castrucci and Associates

Beyond Refractive Optix
Walt Trybula, Sematech

Future Challenges in Silicon
Paolo Gargini, Intel

Outlook for 193-nm Lithography
Paul Brickmeier, SVGL

Synctron Source for X-Ray Point Source Systems
David Andrews, Oxford Instruments

A Fully Integrated X-Ray Point Source System
Robert Selzer, SAL

Current Status of Semiconductor X-Ray Lithography
George A. Gomba, IBM

Lithography Cost of Ownership
Yoshio Gomei, Association of Super-Advanced Electronics Technology

Manufacturing Process Complexity—Photolithography vs. X-Ray Lithography
Wolfgang Liebman, Bio-Tek Instruments

X-Ray/Optical Device Performance
Worth Handley, University of South Florida

TUESDAY, JULY 15

Program Chairs: Jim Harrison, Intel, and Larry Zazzera, 3M

Opening Remarks
Jim Harrison, Intel

The Partnership's First Year
Elizabeth Dutrow, U.S. EPA

Combined Approach to Zero Emitting PECVD Processing
Ken Aitchison, Novellus Systems

Evaluation of C₃F₈ as an Alternative Cleaning Gas in PECVD Processing
Sey Ping Sun, Advanced Micro Devices

Chamber Clean PFC Reduction
Tom Deacon, Applied Materials

Evaluation of TFAA as an Alternative Cleaning Agent in Chamber Clean
Speaker TBA

Permeation Technology Applied to PFC Capture
Gerard Dupois, Air Liquide

Praxair PFC Recovery and Reuse Evaluation at Texas Instruments
Tina Gilliland, Texas Instruments

Closing the C₂F₆ Lifecycle—Recycle
Mike Mocella, DuPont

STEP: Automated Reliability, Availability and Maintainability (ARAM)
8 a.m.–noon

Introduction
Margaret Pratt, Sematech

Introduction to E10
Debra Vogler, Watkins-Johnson

ARAMS State Model, Substate Codes, Data, and Behavior
Margaret Pratt, Sematech

Implementing ARAMS on Equipment
Jack Ghiselli, GW Associates

Overall Equipment Efficiency (OEE) and Capital Productivity Metrics
Terry Ronig, National Semiconductor, and Tom Pmorski, Fairchild Semiconductor

Panel Discussion

Material Characterization Strategy for the Giga-Bit DRAM Era
8 a.m.–12:30 p.m.

Program Chairs: Sookap Hahn, Pacrim Technology, and Sang-il Park, Park Scientific Instruments

Role of Material Characterization in 1997 Metrology Roadmap
Alain Diebold, Sematech

Advanced Defect Identification Requirements and Techniques for Sub-0.35-Micron Process
Homi Fatemi, Norsam Technologies

Challenges in Materials Characterization for the Gigabit DRAM Era
Thomas Shaffner, Texas Instruments

Future of Electrical Test Measurements for DRAM Process Control
Gilbert A. Gruber and Robert Hillard, Solid State Measurements

The Challenges for Analytical Measurements in the Gigabit Regime
Richard Hockett, Charles Evans & Associates

Transmission Electron Microscopy of Integrated Circuits: Strategies for Smaller Geometries
David Su, Philips Semiconductors Materials Analysis Group

Characterizations of Semiconductor Materials and Devices with SPM
Sang-il Park, Park Scientific Instruments

Characterization of Defects in Submicron Device Processes: Nondestructive or Destructive Techniques
Victor Higgs, Bio-Rad Microscience

MEMS Technology Tutorial
8 a.m.–5 p.m.

Instructors: Mehran Mehregany, Case Western Reserve University, and Steven T. Walsh, NJIT

Course outline: Overview of MEMS market, introduction to MEMS, device and application, lunch with guest speaker, materials and processes, and testing and modeling.

Equipment and Materials Market Briefing
8:30–9:30 a.m.
Moscone Center

SEMI Senior Market Analyst Elizabeth Schumann offers a midyear look at the worldwide semiconductor equipment and materials markets. She will discuss microelectronics market trends and outlook, wafer processing equipment, assembly and packaging equipment, test equipment, regional trends, fabrication materials, and more.

Chemical Vapor Deposition (CVD) for Integrated Circuits Tutorial
8:30 a.m.–5:30 p.m.

Instructor: Ted Kamins, Hewlett-Packard

Course outline: Fundamentals of CVD: gas-phase processes, surface process, and plasma-enhanced CVD; CVD equipment reactors, batch and single-wafer associated equipment; and deposited layers for ICs--epitaxial silicon, polycrystalline silicon, dielectrics, metals, and silicides.

Calibration of APIMS Standards Workshop
5–6:30 p.m.

Presented by the APIMS Task Force
Chaired by Jacques Mettes (APIMS Task Force Leader), Meeco

APIMS (atmospheric pressure ionization mass spectrometry) combines extremely low detection limits and very fast response time with the capacity to measure multiple impurities simultaneously. APIMS works in most inert ultra-high-purity (UHP) matrix gases and measures most of the impurities. Calibration is critical to its performance and involves the generation of extremely low traceable concentrations. Various calibration techniques will be presented together with the precision that can be achieved. A special topic in this workshop will be the calibration of moisture.

WEDNESDAY, JULY 16

Program Chair: Eric Marks, Schneider Automation/Square D Co.

Introductory Remarks/Welcome
Eric Marks, Schneider Automation/Square D Co.

Keynote Speech: The Future of MES and Controls
Dick Morley, R. Morley, Inc.

MES: Open Systems for the Semiconductor Industry
Doug Scott, Promis

MES as an Agile Manufacturing Tool
Ralph Zak, Consilium

MES Successes: Integration from ERP to Process Equipment
John Biasi, FASTech Integration

Panel Discussion: Customer Issues and the Value of MES
Moderator: Eric Marks, Schneider Automation/Square D Co.

Panelists: Dick Morley, R. Morley; session speakers; and a special guest

STEP: Recipe Management Standard (SEMI E42-96)
8 a.m.–noon

Introduction
Margaret Pratt, Sematech

Recipe Structure and Attributes
Margaret Pratt, Sematech

Recipe Namespace Management
Speaker TBA

Execution Recipes, Recipe Execution
Speaker TBA

Panel Discussion
Kevin Nguyen, Mitta Technologies; Eric Smith, FASTech; Cathy Wong, Consilium

Global 300-mm Transition Status, Timing, and Related Issues
Session 1—8 a.m.–noon
Session 2—1:30–5 p.m.

The status of the move to 300-mm wafers and the activities of the 300-mm focused consortia and regional organizations will be presented in the first session. In addition, a progress report will update the status of the development of 300-mm wafer, carrier, and interface standards. In the second session, a series of presentations from various disciplines involved in the fab construction industry sector are scheduled. A roundtable discussion will follow to identify issues that challenge IC manufacturers, tool builders, and fab design construction teams to review the current procedures and methods of operation.

Planarization Processes for ULSI Fabrication to the Year 2001 Tutorial
8 a.m.–5 p.m.

Instructors: Frank Kaufman, Cabot, and Dale Hetherington, Sandia National Labs

Course outline: Need for planarization, traditional dielectric planarization (gap-fill, etchback, spin-coating), dielectric planarization by CMP, metal CMP (tungsten vias, damascene, dual damascene), shallow trench isolation by CMP, defects, post-CMP cleaning, the science of CMP, and evolving trends in planarization.

Process Integration and Device Characterization in Microelectronic Manufacturing Tutorial
8 a.m.–5 p.m.

Instructor: Badih El-Kareh, IBM

Course outline; Semiconductor products, trends and scaling, memory, and logic; a typical CMOS process sequence; unit processes--impact on devices and trade-offs; wafer preparation and properties; thin-film deposition; interlevel low-K dielectic; lithography, resolution enhancement techniques; etch, enhancement techniques; ion implantation, extensions to low and high energies; multilevel metallization, planar process; yield considerations, defects and contamination; reliability considerations; and failure mechanisms.

FPD Manufacturing Economics & Technology Update
8 a.m.–4:30 p.m.

Program Chair: Aris Silzars, NorthLight

Opening Remarks
Aris Silzars, NorthLight

FPD Market Overview & Forecast
David Mentley, Stanford Resources

Materials and Equipment Market Overview & Forecast
Bill O'Mara, Bill O'Mara Associates

Equipment Market Session
Microlithography, Nikon; CVD and PVD, AKT; etch, TEL; sputter, coating and cleaning, DNS; test and repair, Photon Dynamics; and material handling, AGI

Manufacturing Processes Session
AMLCD, Toshiba; PDP, NEC; and FED, Candescent

FPD Manufacturing Economics: Taking Your Idea to the Market
Aris Silzars, NorthLight

(Other offerings in San Francisco this year include courses on semiconductor processing technology, management of new product introductions, ergonomic design for 200- and 300-mm wafer processing, customer satisfaction, CE marking forum, improving tool productivity, cost of ownership, the Lancaster equation, and market forecasting techniques. Call SEMI at 415/940-6905, or check SEMI OnLine at www.semi.org for more information on the San Francisco schedule or the San Jose offerings.)

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