ANALYSIS AND METROLOGY — DEFECT DATA

Using SSA to measure the efficacy of automated defect data gathering

Kenneth W. Tobin, Shaun S. Gleason, and Thomas P. Karnowski, Oak Ridge National Laboratory;  and David Guidry, Knights Technology

Process- and equipment-generated defects must be reduced in order to meet future yield targets, according to the latest National Technology Roadmap for Semiconductors. The document emphasizes the importance of continued development and availability of automated defect detection, review, and classification technologies. These new analytical tools will help engineers quickly assimilate manufacturing data from defect inspection tools, and translate those data into manufacturing solutions that enhance device yield, reliability, and performance.¹ The rapid collection and analysis of semiconductor wafer defect data are absolutely essential to understanding and controlling the contamination sources and process faults that affect product yield.² However, device manufacturers face a major challenge in figuring out how to convert the massive amounts of process data into useful process control information that will have a positive impact on time to market, product ramp-up time, and wafer fabrication revenue.

In response to this challenge, a new technology has been developed to automate the interpretation of product-wafer defect data—spatial signature analysis (SSA). Developed under a cooperative R&D agreement between the Image Science and Machine Vision Group of the Oak Ridge National Laboratory (ORNL; Oak Ridge, TN) and the Contamination Free Manufacturing Research Center at Sematech (Austin, TX), SSA is an artificial intelligence method that effectively deals with the issue of intelligent data reduction and delivers timely manufacturing feedback.³

The SSA technology has been licensed and commercialized by Knights Technology (Sunnyvale, CA) under the trade name SPaR, for spatial pattern recognition software. Designed to help engineers diagnose the root causes of wafer processing defects, this automated method detects and classifies wafer anomalies based on wafer-map defect distributions. The software uses computer vision algorithms and extraction techniques for pattern analysis to accurately identify and classify defect patterns. The defect wafer maps are then transformed into a summary of process events that can help engineers predict and prevent yield loss. By reducing the cost and time needed to identify the root causes of a manufacturing defect, the software therefore minimizes the amount of defective product made before corrective actions are taken in the manufacturing processes.

Automated Defect Data Analysis

Image-based defect detection workstations produce and store tremendous amounts of data that are costly and time-consuming to evaluate by the manual inspection of wafer maps. SSA technology automates the identification and classification of these data, transforming defect wafer maps into a summary of process events. Defect and yield engineers can use the software to import wafer-map data generated by standard inspection tools, then analyze and automatically group and sort the defect patterns into unique classified signatures. The software has the ability to analyze very sparse, broadly distributed signatures and to intelligently connect and track tightly grouped clusters into common source events. This results in the grouping of distinct defect signature populations deposited by or created from a single manufacturing source.

Advanced Defect Clustering. The wafer-map signature classification process begins at a very basic level with the locating and grouping or clustering of defects. Clustering techniques used by most commercial in-line inspection tools and defect data management systems are limited to clustering defects that are geographically close together on a wafer map. The advanced clustering paradigm used by the SSA technology combines classical defect-clustering techniques with unique morphological dilation and fuzzy rule algorithms to group shapes into objects and to assign object membership to high-level classes, as shown in Figure 1.

Figure 1: Fuzzy rules are used to combine shapes into objects and to assign object membership to high-level classes.

The ability to group defects from a stack of wafers from one lot or across lots into a signature is a powerful way to find subtle problems. The composite wafer map shown in Figure 2 comes from a group of single wafer maps after a CVD process. It tells the engineers that 617 defects fit together and are caused by the same process contamination problem. Several examples of spatial signatures are also presented in the figure.

Figure 2: Automated spatial signature analysis is a powerful way to group defects.

The software analyzes more than 60 features that describe a signature, such as scale, density, distribution, orientation, extent, and overlap. It assumes that every connected or distributed object—an element of a process signature—can be categorized into one of four sets according to its morphology and proximity to neighboring clusters.⁴ Figure 3 includes representative maps of the sets, which are described as curvilinear, amorphous, global, and microstructure.

Figure 3: Process signature element classifications (from left to right): curvilinear, amorphous, global, microstructure.

Signature Classification. The software's automatic data collection and analysis technology goes beyond the mere sorting and storing of defect signatures and characteristics. By use of an established library of signatures, the defect patterns are classified into process categories or events. Figures 4a and 4b show examples of defect signatures. Recurring defect distributions that do not form discrete cluster patterns can also be analyzed. On-line process characterization enables engineers to relate specific defect shapes or patterns to process-related, real-time causes, which immediately provide critical defect source information.

Figure 4: (a) Examples of mechanically induced defect signatures found by the SSA-based software; (b) examples of random and systematic signature types found by the SSA-based software.

Signature Analysis Library

Defects are first identified and grouped into a signature. Figure 5 shows six classes of signatures characterized using the 60 features. Because proper training of the classifier is critical to the system's functionality, a combination of fuzzy logic measurements that are displayed through symbols, text, and color help the user quickly identify and mitigate possible data conflicts. Intermediate imagery is available that details various steps in the analysis process so the user can isolate and troubleshoot training problems. Once an adequate training set has been established, the software can automatically segment and classify multiple signatures from a standard electronic wafer-map file into user-defined classifications. The automatic classifier uses human expert knowledge to learn how to trace manufacturing problems to their source without experiencing the drawbacks associated with human inspection, such as fatigue or inexperience.

Figure 5: Semiconductor wafer signature examples.

Library Generation. Based on tool-specific experiences, the reference library of known signatures is constructed over time. Users can add to their signature library by adding old signatures to it. Output files saved from previously processed wafer maps can be added to the library and included in the classification and naming procedure. Each library signature is represented by a picture of its defects, and the user can display galleries of each library class. Signatures can be easily moved and deleted from a class. Improving the ease-of-use efficiency and accuracy of library generation will be a key element of future upgrades to the software package.

Enhancing Defect Data Analysis. Determining the source of a defect has long required the review of defect data from both high-resolution images of individual defects and low-resolution defect wafer maps from in-line inspection tools. Because the wafer-map analysis had to be performed manually, engineers had to examine large numbers of defects to characterize a whole wafer. The automation of this once-tedious process is a key to attaining the industry's yield enhancement goals. With the SSA-based software, yield engineers can automatically characterize a wafer into known problems, unclassified signatures, and random defects. Then, by sampling a subset of the unclassified signatures and random defects for off-line or automatic defect characterization (ADC) review, the entire wafer can be more completely characterized with fewer reviewed defects. This more-complete analysis of the results from defect inspection allows manufacturers to reduce the utilization of time-consuming and costly ADC review stations.

Theory to Practice

The development of SSA technology by ORNL and Sematech researchers was an outgrowth of their original charter to ascertain the state of the art of defect classification technologies. To develop the initial algorithms for signature segmentation and subsequent classification, the researchers interviewed fabrication engineers and reviewed more than 2000 wafer-map files donated by the consortium's member companies. When the development phase of the project was completed, the researchers conducted a validation exercise with a threefold purpose:

• Quantify the performance of the SSA technology's advanced clustering and defect classifier features in the manufacturing environment.

• Gather user information to guide revisions of the initial algorithm in order to accommodate a wide spectrum of manufacturing circumstances.

• Help set the industry's direction for continued research and development.²

Rationale. All SSA capabilities depend on two key technologies: advanced clustering and signature classification. Because of this, the performance of these technologies was seen to be critical to the technique's ability to trace the identified signatures to known process problems and deliver the necessary information for the efficient application of statistical process control (SPC) functions.

Methodology. The validation exercise was a five-month test of the maturity of the SSA technology research and the SSA C++ software library in three different manufacturing environments on three separate products: ASIC, DRAM, and SRAM (see Figure 6). The software was installed in early 1997 at three Sematech member companies selected as sites for the validation exercise. Wafer maps were processed as an automated background process at two sites and manually at one. Once a week the data at each site were analyzed and critiqued by fab engineers.

Figure 6: Validation exercise experimental design.

Results. Both classifier and clustering performances were measured. The performance data for this exercise, detailed in Figure 7, were gathered from multiple wafer lots and process layers. In Figure 7a, overall wafers in set refers to the average performance for all data analyzed in each category at each site. These data reveal that the SSA classifier and clustering technology is effective about 76% of the time. A dominant signature is the critical or most relevant signature on the wafer as defined by the yield engineer and, therefore, reveals the most details about the manufacturing process.² The classifier performance was higher in this category than overall, and the clustering performance of 100% in the same category was particularly impressive.

Figure 7: Clustering and classifier performance data for wafers analyzed at fab sites.

These data indicate that the SSA technology successfully detects and identifies the key signatures most likely to provide meaningful insight into the manufacturing process and to lead to rapid process characterization and correction. These data were obtained from a broad range of products, processes, and manufacturing cultures. As a result, even better classifier performance can be expected when SSA is focused on specific processes, layers, and products at a specific fabrication site.

The balance of the performance data, shown in Figure 7b, reflects the classifier and clustering capabilities of SSA for various whole-wafer defect levels. The classifier data suggest an essentially uniform distribution of performance across all wafer defect densities. However, the efficacy of clustering performance decreased as the density of wafer defects increased. The researchers believe that this performance degradation is the result of confusion caused by an increasing number of high-density, overlapping signature events.²

Increasing Fab Productivity

The software package's automation technology represents a major improvement in data analysis for semiconductor manufacturing. It will have an impact on many analyses that are now performed manually or not at all, including:

• Automatic analysis of wafer maps arriving from in-line tools. This analysis will result in fast determination of the root causes of manufacturing problems that otherwise would have a continued negative impact on wafer processing.

• Improved SPC resolution by providing new ways to track manufacturing events for control charts. The events could include random and systematic defect populations, scratches, streaks, and stains, among others. Current SPC tracks only total or cluster defects, although clusters are rarely significant unless organized into signatures.

• Efficient off-line review. The use of intelligent sampling improves off-line automatic defect classification performance. The ability to automatically generate a reference library of known signatures helps complete defect review and analysis tasks faster and more efficiently.

• Improved process yield. Near real-time signature information enhances the prediction and prevention of yield loss.

Integrating Automated Analysis. The software can automate several defect-based monitoring processes. Figure 8 illustrates how the software can be integrated into the manufacturing and data-sampling process, the storage and management of process and product data, and the analysis and sourcing of defect information for manufacturing control. The first anticipated role for the SSA-based software is the automation of wafer-map analysis to quickly source manufacturing problems based on common signature patterns. In Figure 8, the lines emanating from the wafer-map analysis station represent functions that are manually monitored but would lend themselves well to automation. For example, the highly detailed system descriptions will deliver new information for SPC functions, including counts of systematic or random distributions of particles; simple and complex scratches, streaks, and clusters; and a variety of other signature types defined by the user through training. In addition, by automatically prequalifying defect data based on the signature type, fewer wafers are required for off-line review than with the older methods.

Figure 8: The interconnectivity of semiconductor fabrication, inspection, and data management.

While other defect distributions may still require off-line review to determine the particle contamination source, the software can provide an efficient sampling plan based on the signature result, which will reduce the number of revisited sites. As a result, wafer throughput on off-line review tools will be increased.⁵

Conclusion

Spatial signature analysis provides semiconductor manufacturers with a new level of information, information that is increasingly critical for controlling the manufacturing process and quickly understanding and correcting important yield issues. The integration of product and process data into an automated analysis environment facilitates a significant increase in yield management capabilities. Results of such automated defect data capabilities include improved wafer throughput in the fab, rapid root-cause determination, high-resolution SPC, real-time yield analysis, and automatic tool control. Recent research efforts to validate the technology have demonstrated that the SSA-based SPaR software is a valuable tool for meeting future yield targets through the reduction of process- and equipment-generated defects.

References

1. The National Technology Roadmap for Semiconductors, San Jose, SIA, pp 153—173, 1997.

2. Tobin K, Gleason S, Lakhani F, and Bennett M, "Automated Analysis for Rapid Defect Sourcing and Yield Learning," Oak Ridge, TN, Oak Ridge National Laboratory, October 1997.

3. Gleason SS, Tobin KW, and Karnowski TP, "Spatial Signature Analysis of Semiconductor Defects," Solid State Technology, 39(7):127—136, 1996.

4. Tobin KW, Gleason SS, Karnowski TP, and Bennett MH, "An Image Paradigm for Semiconductor Defect Data Reduction," presented at SPIE 1996 International Symposium on Microlithography, Santa Clara, CA, March 1996.

5. Tobin KW, "Semiconductor Spatial Signature Analysis (SSA)," Oak Ridge, TN, Oak Ridge National Laboratory, 1994.

Kenneth W. Tobin, PhD, leads the Image Science and Machine Vision Group at Oak Ridge National Laboratory (ORNL), Oak Ridge, TN. His technical research includes scene analysis and pattern recognition for machine vision as applied to industrial real-time, high-speed inspection, and automation problems. He has been doing research with the semiconductor industry since 1991, performing R&D for optical image defect classification and electronic wafer-map spatial signature analysis and data reduction. He has authored or coauthored more than 50 technical publications in the areas of nondestructive test and analysis, signal and image processing, and pattern recognition. Tobin is a member of the Optical Society of America and the International Society for Optical Engineering (SPIE), where he is a cochairman for the SPIE Conference on Machine Vision Applications in Industrial Inspection. He is also a member of the Defect Reduction Crosscut Technology Working Group for SIA's National Technology Roadmap for Semiconductors. He has a BS in physics and an MS in nuclear engineering from Virginia Polytechnic Institute (Blacksburg) as well as a PhD in nuclear engineering from the University of Virginia (Charlottesville). (Tobin can be reached at 423/574-8521.)

Shaun S. Gleason is an R&D staff member with the Image Science and Machine Vision Group at ORNL. He researches algorithm development and has authored or coauthored 21 publications in the areas of image processing, feature extraction and analysis, and pattern recognition. Since 1991, Gleason has worked in the area of automated semiconductor defect inspection with Sematech, specializing in automated defect classification and spatial signature analysis. He has a BSEE and MSEE from the University of Tennessee (Knoxville) and is a PhD candidate.

Thomas P. Karnowski has been an engineer with the instrumentation and controls division at ORNL since 1990. His research interests include image enhancement, data visualization, and cognitive systems. He received a BSEE from the University of Tennessee (Knoxville) and an MSEE from North Carolina State University (Raleigh).

David Guidry is a product manager for the Knights Technology division of Electroglas (Sunnyvale, CA). He has more than 10 years' experience in the semiconductor business as a process engineer, product engineer, device engineer, process transfer engineer, and mainly as a yield enhancement engineer. Before joining Knights, he worked at Advanced Micro Devices, Philips, and Altera. He received a BS in chemical engineering from UC Berkeley and an MBA from the London Business School, where he concentrated on marketing and strategy. (Guidry can be reached at 408/988-0600.)

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