Editor's Page

The copper connection

The semiconductor industry faces a daunting array of defect reduction and yield enhancement challenges as it implements copper and low-k materials and processes over the next couple of years. The SIA roadmap noted that yield losses caused by contamination-related defects and field failures in the interconnect modules at the back end of the line will continue to outnumber those found in all the other process areas combined. Detecting ultrasmall particles and transparent dielectric scratches as well as defects in multilayered films, setting realistic defectivity targets, finding submerged voids, normalizing new materials and structures, regulating new CMP and etch parameters, and implementing trace-level, real-time metrology all rate high on the list of key manufacturing and technological issues in the new era of interconnection.

Because of the importance and relevance of this rapidly emerging copper chipmaking age, MICRO will feature an exclusive yearlong technical article series in 1999 entitled "Building Copperopolis." California history buffs may recognize the name as that of a once-booming mining town in Calaveras County, the same county where a jumping frog contest inspired Mark Twain to write one of his popular early stories. My choice of this title has little to do with some esoteric connection between the boom-and-bust cycles of the former copper lode with the economic slings and arrows endured by the semiconductor industry. Instead, the sound of the word Copperopolis summons visions of grandeur, of humankind's ability to create monuments to its own inventiveness. While there is no consensus on how quickly copper interconnect technology will change the face of chipmaking, there is almost universal agreement that it will. This monumental evolution in the way semiconductors are made deserves an appropriate moniker, hence Copperopolis.

This series will feature technical articles from the equipment and materials suppliers as well as the research and chipmaker communities. Topics will include defect analysis and metrology, chemical and slurry delivery and waste treatment, process equipment defectivity, surface cleaning, and more. The first installment in this issue focuses on CMP and post-CMP cleaning issues for dual-damascene copper technology from the perspective of a leading process chemical and slurry manufacturer. The next installment in our March issue will detail the use of TOF-SIMS for the inspection of residual metallic contamination on patterned copper interconnect wafers with a tie-in to post-CMP cleans.

The other series of note in '99, "Extreme Silicon," begins in February. It deals with some of the technical challenges faced in the wafermaking side of the industry. Few segments of the semiconductor business must balance the combination of intense technological and economic pressures as much as the wafer community does. Although their products are increasingly viewed as commodities, they must provide leading-edge technical services and support, regardless of the fact that they carry the burden of one of the tightest profit margins in the business. The articles are based on work done by Larry Shive's cleaning, inspection, and packaging R&D team at one of the hotbeds of wafermaking, MEMC Electronic Materials' St. Peters plant near St. Louis. As you will see, the wafer folks have a lot of solid technical information to share with the chip fab rats and their other suppliers.

In addition to this year's featured article series, we will continue our long-running tradition of providing in-depth articles on other technical topics of note as well as cover the waterfront with timely industry news and product coverage, both in the print version of the magazine and here at www.micromagazine.com. I welcome your input as we approach Y2K and beyond.

Tom Cheyney
Editor
tom.cheyney@cancom.com