EDITOR'S PAGE

In the rough at Pebble Beach

The nerves of the economic forecasters covering the semiconductor industry have become increasingly frayed these past few years. During guardedly optimistic prognostications for 1999 from the numbers guys at SEMI's recent Industry Strategy Symposium in Pebble Beach, there were direct and indirect admissions of screw-ups predicting the 1998 stats for the chipmakers as well as their tool and materials suppliers. A quick cross-check of last year's conference notebook found projections off by as much as 50 percentage points, certainly not the kind of accuracy that enhances job security for market researchers and internal company planners.

Clark Fuhs of Dataquest and Dan Hutcheson of VLSI Research reprised their mano a mano analyses of the year in review, the year ahead, and the next five years for the wafer fab equipment crowd. Hutcheson said that for 15 years leading up to 1995, his forecasts had an average error rate of 5.6%, but since then "pandemonium" has set in and the numbers have been all over the map, forcing a monthly data reevaluation. For example, VLSI's 1998 forecast evolved from a booming 20.6% in September 1997 to a crashing —26.6% as of December 1998. Fuhs's numbers were less dodgy, with his forecast of 2% growth at last year's ISS off by only 25 percentage points or so. After removing the crow from their mouths, the two speakers' growth projections for the capital equipment sector veered toward the cautious this time, with Dataquest citing a —1.7% rate and VLSI's best guess edging into the black at 1.2%. Both agree the cycle has bottomed out, with the end of 1999 and 2000 heralding the end of DRAM overcapacity and a return to profitability for the tool suppliers. The assorted 1999 chip industry forecasts aired at ISS ranged from a mid-single-digit to low-double-digit uptick, while veteran market watcher Dan Rose predicted 5.6% growth in the wafer fab materials segment after a year in which it posted its worst decline since 1985.

Technology presentations continued to be an essential part of the ISS schedule, with Suresh Venkatesan of Motorola delivering the keynote. His talk focused on the unprecedented "materials revolution" at hand. He discussed the increasing dependence on high-end photomasks and the looming postoptical lithography era, more evolved device design considerations, new gate dielectrics, and the process integration conundrums of multilevel metallization, especially those encountered with the introduction of copper and low-k materials. Venkatesan said that one crucial challenge facing users and suppliers alike is the need to sustain R&D and amalgamate process and equipment, and to do so in sync with the new materials introduced at each successive technology node. One of his recurring themes was the need for improved defect reduction tools and more innovative yield improvement techniques, from tackling such relatively new killers as "floating body effects" and "voltage contrast defects" to developing effective failure analysis—driven yield enhancement methodologies. TI's Venu Menon covered such process control and yield management topics in more detail during his talk. He listed gate critical dimensions, CMP, film thickness, and interconnect defects as key process control areas, while challenging the SEMI members in the room to move yield learning into the equipment and process development phase.

This year's ISS not only demonstrated the increasingly tricky art of forecasting the economics of the semiconductor industry but also underscored the increased interdependency of chipmakers and their suppliers.

Tom Cheyney
Editor
tom.cheyney@cancom.com