INDUSTRY NEWS

FACILITY UPDATE

Applied gets modular with new process integration concept

SANTA CLARA, CA—"How do we mimic how our customers will use their processes so they'll get more-mature machines for their needs?" asks Dennis Yost, director of Applied Materials' process sequence integration (PSI) division. His company's answer to this billion-dollar question is the new EPIC, or Equipment and Process Integration Center, occupying buildings 3 and 89 at Applied's international headquarters site. EPIC officially opened in early November, although it was on-line in August. The company's "first fully integrated and electrically characterized process module" developed at the pilot-line facility will be its copper interconnect equipment set, which can fabricate a complete dual-damascene multilevel structure.

Building 3 houses 28 tool bays, all 300-mm-compatible, 10 of which are dedicated to the copper program. The entire Applied copper and low-k product line fills the bays—from etch and CMP to low-k dielectric film, barrier/seed copper, and an as-yet-unnamed electrochemical plating unit. A large suite of analysis, metrology, and wet-process equipment also resides in this building, including defect detection and review stations from the company's process diagnostics and control (PDC) group and state-of-the-art electrical characterization tools. A lithography cell occupies nearby Building 89, which is a converted office space. An ASML 5500/90 DUV stepper and DNS 80B track are the main occupants, with a wafer particle inspection tool, an overlay registration instrument, a CD-SEM, and a resist strip tool among the assorted support equipment. The two buildings have about 9000 sq ft of cleanroom space between them, with minienvironments creating Class 1 conditions in key locations.

About 30 people work in the facility, with another 50 people actively involved from Applied's product groups—"where they're working on the tools, and we're running the process," says director of operations John Egermeier. "Our process integration effort operates like a fab. We have a production meeting every day at 4 p.m., and we go through all the lots and prioritize them, we argue about technical merits, and so forth. It's very fablike."

"We want to enable our customers to get a process module and equipment set solution that's significantly more mature than they used to get," explains Yost. "What we're trying to do is give everyone a level of capability that proves out the equipment set and the performance. Then they can internalize it into their facility and make it their own proprietary technology. So here's the precompetitive process flow, you know it works, you've got this level of performance. You're going to tweak and modify the process flow to meet your specific needs, to give you your competitive differentiation. Customers can bring their wafers, run the interconnect on them, and then go evaluate them. We don't have any plans for doing production for customers here, but really to help them develop and demonstrate the technology." To back up its claims, Applied guarantees each module for defects, operational cost and productivity, and electrical performance.

EPIC's lithography tool set has full patterning capability down to 0.18 µm and is supported by a host of metrology equipment. Photo by Charles Lewis

Once a module is developed, Yost says, a dedicated "transfer team" of 10 specialists will go and support the customer at its site all the way through qualification, "to make sure that the entire module works together. Some will be skilled in certain areas—etch, CMP, deposition—and some will be skilled in the overall module and what the electrical performance means, as related to the individual processes. They will be responsible for what I call 'cradle to grave' of that particular technology for the customer." The first module is scheduled for customer delivery sometime in the spring, according to Yost.

Obviously, different customers have different needs, so the number of wafers and amount of time it takes to ready the process module will vary, as the PSI director explains. "We're planning to have a baseline capability that we demonstrate and continuously run, with our internal test chips." (Applied's five-level metal design test chips were developed in collaboration with TestChip Technologies and Sandia Technologies, two of the equipment giant's partners.) "So that's always running, we always understand the test data, we're always improving the performance on it. A customer may come in and run anywhere between three and six demo lots, and if they all meet their performance criteria, then we would start the transfer mechanism. We plan on running a 20-day cycle time per lot, so in order to accomplish three to six development cycles, we're talking less than two months."

One of the key capabilities at EPIC is its combination of defect and electrical test toolsets. "We can do in-line defect inspection and correlate it to electrical test," says Yost. "We can really focus on the electrical defect density, which equates to yield for our customers, so they can start off at a more-mature integrated module of performance."

The efforts of the PDC defect team mirror those of a yield group in a chip fab, with some important differences, says Andy Skumanich, strategic marketing and advanced technology specialist for wafer defect reduction systems. "We're trying to develop information that goes to root causes much more rapidly. Since we're working in tandem with the tools, we have a much tighter connection, so we'll see more as they're developing tools. We have a project with metal etch, where we're using our [defect] tools to help them define their BKMs, or best known methods. We've got a much tighter connection than, say, the yield enhancement people at a fab. They have the defect people who catch the defects, and they have to figure out what the defects are, do the analysis, try to determine which tools or materials are doing it, and the potential sources. To do that, they have to call in the AMAT person, the Lam guy, the materials vendor, or whomever to try and understand what could be the potential sources. Then you try and tweak those, talk with the vendors, hopefully get the improvements or corrective actions, go back, rerun, reinspect, and so forth. As you can see, that's quite a process.

"What we're trying to do is cut that down to where BKMs are taking care of things for the customers. We expect to build a library of defect sources and potential root problems and remedies, so that they have a faster time getting the tool back on-line. You can talk about the goal of high yield resulting from defect inspection but there's a potential hidden point there: you might find that one of the tools has a problem, so you turn it off. Your yield is still high, but the tool is sitting unused because you can't figure out what's going on. You have high yield but low utility. What we want to achieve is high yield and high OEE [overall equipment effectiveness] at the same time. That's where we are different from just a yield enhancement team."

The PDC group is also expanding its internal role in other ways through its work at EPIC, says Skumanich. "We'll be using the tools in a yield-management function within the company, combining the integration knowledge as well as the information systems we'll be generating. EPIC will be an alpha site to develop the info systems required to handle gigabytes of data a day, which is what will be dumping out of this while we're ramping the defects down."

The semisecret weapon at the back end of the pilot line is what Egermeier calls the "most advanced tester in the world," a customized Hewlett-Packard 4071 DC tester, equipped with a high-temperature wafer-level reliability option. "To do electromigration tests on the wafer," continues the operations director, "when you go to copper, you're using a lot more power [than on aluminum]. So we had to get HP to boost the power on a sense measurement unit card; that pushes it so we can do wide-line copper electromigration testing. The idea is, on the wafer level, to get a six-week test squeezed down into a couple of hours. We're using software from Sandia Technologies, who teamed with HP to come up with a way to accelerate electromigration testing. The Electroglas prober and the tester make up the essence of our electrical test capability, which is the entire feedback loop."

Egermeier elaborates on one example where the tester proves its mettle—chemical-mechanical polishing. "If we're going to etch to a certain depth everywhere across the wafer, then later we're going to do CMP, and with CMP we're going to remove some of the oxide, and on top of that, we're going to remove the copper. So if we can do that uniformly across the wafer, that determines the actual thickness of the metal wires. Whereas if we're doing metal etch, we can deposit within 10 angstroms of the required thickness, and then the only linewidth control is the CD, in photolithography. Now I've got CD on my etch, then I have a depth issue on my etch, then how much of the oxide did I remove when I did CMP? So I've got three inputs into the electrical linewidth, and if you don't have a tester, then you can't get the CMP process optimized to the etch process.

"When we started, the first lots that came out had 40% electrical linewidth variability, and from our CMP, we had a one-step process. Then using that feedback, Greg's group [Greg Amico, CMP global product manager] was able to develop a three-step process that gives better than 10% across-the-wafer electrical linewidth variability."

Amico cites examples of the benefits of the integration work for his group. "Some defect issues start before CMP, because at the edge of the wafer, depending on how the liner and electroplating are deposited, there can be an effect on the CMP process. If all that isn't integrated well, we get peeling at the edge, which we have seen on some wafers. Then that starts scratching the wafers. So it really starts back there. That's one of the areas PSI will focus on: the integration at the edge of the wafer, with our liner and electroplating process and then our CMP, so we can ensure that, with this module, you won't have peeling.

Defect detection stations (left) bolster yield-management efforts, while minienvironments (below) provide Class 1 conditions at key locations inside EPIC. Photos by Charles Lewis

"Another area is making sure the wafers are properly treated and passivated coming in. If a customer is using a stand-alone system, then typically the wafers sit in the DI-water tank. We found that, depending on how you treat the wafers, how long you leave them in the tank, there could be a corrosion issue, which has to be addressed. So that would be more from just a fab logistics standpoint, in knowing what you had to do in electroplating, and then what kind of delay times you can have pre-CMP and post-CMP to avoid that issue. And as for corrosion, it is tied up in how you process in the tool and adding the proper additives to the slurry, and then how you process before and after. That's another area we have been involved with in PSI: After we've done polishing, how do we handle the wafer, go to the next step, and avoid corrosion issues? We're also working with the PSI group to qualify our dry-in, dry-out solution."

One of EPIC's unique features is what the company calls a "complete, closed-loop waste abatement system that removes all traces of copper from the facility's effluent stream." The custom system, developed with Hydromatics, "takes all copper out of the liquids, puts it into a solid source, and that's what's hauled away and disposed of," explains PSI head Yost. Through novel filtration and ion exchange modules, all copper-bearing aqueous solutions are turned into DI water, which is then funneled back into the facility and reused.

"We're hoarding our water molecules," quips Egermeier. "We don't have to pay for any sewer discharge permit, don't have to buy a lot of water. The only costs we have are in the operation of the filter and the regeneration loop, where we take some chemicals and put them into an ion exchanger every so often. This does generate some toxic liquid waste, but we boil the water off of that and create copper salts, which is solid waste. There's some labor here, and that's it. This is going to be the lowest cost system of any that our customers can get."

Customers won't be the only ones to potentially profit from Applied's equipment and process integration strategy. The company expects to reap benefits in terms of improved product development and shorter time to commercialization of its tools. "EPIC's going to impact the product development cycle time dramatically," says Egermeier. "We won't have to wait for the customer wafer, process it, send it back for patterning, and maybe get it back a few weeks later. For the first time, we'll be using internal wafers, saving our customers the extra time and cost of sending us large numbers of their wafers, so we'll have the flexibility for real process development. . . . We'll be able to understand the process sooner and concentrate on maximizing our performance sooner. So instead of running around dealing with a bunch of field and spec issues, by the time the CMP or etch tools are in production, we're already going to have a chance to rotorooter any problems here."

Yost succinctly reiterates the goals of Applied's EPIC strategy. "Reduce the risk for our customers, accelerate their time to market, and lower their cost by enabling their technology. There is a single point of accountability for the entire process module. I remind our customers," 'There's only one neck you have to put your hands around.'"—Tom Cheyney

Lead photo by John Spangler