INDUSTRY NEWS

Reliability, defect concerns slow rush to rapid copper integration

N early two years into the copper rush, the trickle of data has become a steady flow of practical information on real-world issues such as defects, yields, and reliability. IBM aside, for most players the information reinforces the steady-as-she-goes approach the industry has adopted as it copes with these issues. Widespread use of copper, historically seen as the natural-born killer defect, is coming around, but perhaps not as quickly as some had originally expected.

"I guess the one surprise following the initial IBM announcement was the response from the industry in terms of the number of people...who said copper was going to be a no-brainer," notes Rod Kistler, director of R&D technology at Cabot Microelectronics Materials, a major manufacturer of CMP slurries. "Having spent 18 months on it, people are realizing it's not such a no-brainer. The introduction of copper is not going to be as aggressive as they first had thought." At the moment chipmakers are reserving the use of copper process for chips in "high-end applications," he asserts.

INTERMETAL: As more data come in, some see copper poised for a major breakthrough. Photo courtesy of Sematech.

Kistler added that Cabot was to announce a new customer at Semicon Korea in late February. The client is a large Taiwanese foundry. "From our perspective, we have different tiers of customers, some more sophisticated than others," he continues. "The early leaders in copper technology are now producing commercial-grade parts that they're selling. Apple has made an announcement that they're now incorporating copper-based microprocessors into their product lines. We are supplying our materials to three such customers doing commercial-grade copper interconnect devices. Two are in North America and one is in the Far East. We expect to double that number, probably within the next six months."

Peter Nunan, director of copper process integration at IPEC-Planar, says the amount of work on the technology depends to a great extent on company cultures. "It's going extremely aggressively with certain people we work with, and I feel some people are behind."

He likens the acceptance level among customers to the shape of a bell-curve distribution graph. His company, which makes the polishers so important to copper integration, is completing a merger with former competitor SpeedFam International. He says "the more aggressive companies" in the copper rush are buying IPEC's 776 system, a dry-in/dry-out tool.

Is IPEC learning anything from clients aggressively pursuing copper integration? "Oh, God, yes," Nunan responds. "The information and learning have gone up exponentially in the last six months. It's taking a long time to light the fuse.

"We know how to do copper now, and now we're working with the real problems," he continues. "You're getting beat up like its tungsten now." As for defectivity matters, we don't get a lot of feedback. [Customers] are not coming up with KLA defectivity maps saying, 'Look. This is from your tool,' which is a great thing. If there are major problems they're not blaming them on us."

One major concern is the effect of erosion "and how it amplifies as you stack up metal layers. The big question is, should we polish interlevel dielectrics? The evolutionary scale is to polish in the beginning and work to eliminate it by improving the copper. It's an integration trade-off if it works well."

Nunan believes it's a mistake to move too fast. "If you try to output low-k no-polish intermetal dielectric and dual damascene all at the same time, you end up with a major leap forward and it's hard to determine where your problems came from. Were they integration problems, or were they just process problems? People are taking a nice conservative evolutionary approach. I think it's right on track."

Nunan predicts the level of activity will increase in the fourth quarter of 1999. "I think that it's definitely going to accelerate. The more people jump in earlier there's a lot more pressure to speed up the introduction of copper."

"I think there are still issues to be worked out," says Cabot's Kistler. One of the challenges is "to manufacture a single slurry chemistry that sufficiently polishes both the copper and tantalum-based barrier films." The barriers are, of course, are a key part of the technology for keeping the copper lines from leaching into the silicon and affecting transistor performance.

Cabot is developing a "multistep process" with a special chemistry for polishing the copper and a separate chemistry for polishing barrier layers. Kistler calls this "the most elegant solution at this point."

None of the defect issues relating to CMP are really new, he says, although polishing tantalum can present a problem. "It depends on the [slurry] chemistry. We are seeing that the tantalum doesn't abrade away like a typical material. What you tend to see is more grain dislocation and pull-out." The hard material "comes out in pieces" that can cause microscratches and pitting on dielectric surfaces. "It is something that we're looking at. It may or may not require a short buff step of the insulator to remove some of that microdefectivity."

The notion that anyone believed copper integration would be a stroll in the garden surprises Martin Manley, director of device and process integration at VLSI Technology. The San Jose—based chipmaker plans to phase in copper interconnect process technology for its devices later this year. The copper will be available for fourth- and fifth-level metal in VLSI's 0.15-µm-linewidth process, the VSC11. "For ourselves, we've never seen this as a slam dunk," Manley says. "I'm surprised to hear that."

"On the one hand you have IBM...actively pushing copper, and on the other hand companies like Intel are saying that at 0.18-µm [geometries] they can achieve 1-gigahertz performance," says Dipu Pramanik, director of simulation and advanced methodologies for VLSI.

"Every time you introduce a new material...it takes one and a half to two years to get over the issues," Pramanik points out. "You're dealing with fundamentally different changes going from aluminum to copper—different slurries, different process models." He says manufacturers face a two-year learning curve, adding, "That's one reason we have this phased approach."

In San Jose, VLSI has set up an 8-in. prototype line with a separate room for the copper-based equipment. "Obviously, a lot of protocols have to be followed. This involved just making sure you don't contaminate wafers by using the same boats. One of the things IBM showed very clearly is that copper will come back and contaminate silicon and have all sorts of leakage problems.

"The biggest problem is with the wafer carriers. You want to ensure that you don't mix up the two," says Pramanik. He adds that VLSI already isolates its CMP area from the rest of the fab with "a separate room and separate drainage and air handling. We just do the same thing for copper." Shared metrology tools in post-CMP processes and the need to develop "sufficient backside cleaning" to prevent copper diffusion are two potential stumbling blocks, Pramanik says.

As of mid-February, no customer had yet asked for the VLSI chip with the dual copper levels. "Customers ask for a certain performance, and it's up to us to decide the best and most effective way of achieving that," Pramanik says. Manley points to the widely held view that semiconductors at the 0.18-µm technology node "can go to high levels of performance with aluminum."

"There's such a thing as being too early and such a thing as being too late," he continues. "At this generation it's very marginal as to whether [copper] is going to be needed at 0.18 µm. Strategically, the advantage is much more pronounced at the upper layers of metal."

IBM announced September 1 that it shipped the world's first copper-based microprocessors, and at least a dozen other chipmakers have weighed in with their copper plans. The number of equipment and materials companies announcing mergers or copper programs has also grown exponentially. These include Novellus Systems, which unveiled its Damascus copper deposition technology last year, as well as its alliance with Lam Research and IPEC; Applied Materials with its EPIC facility and tool set in Santa Clara, CA; and Semitool and SpeedFam, which recently announced plans to cooperate on the development of integrated solutions for copper interconnects, complimenting Semitool's alliance with Ulvac, which focuses on barrier materials.

The consensus, then, seems to be there will be no earth-shattering epiphanies on what has been dubbed by one company "the road to damascene." The real problems with contamination and reliability will begin at 0.2-µm geometries and below, points out Dennis Yost, director of the process sequence integration group at Applied Materials. "People do more monitoring of tools—here at Applied, too—to make sure that the baseline process works. You want to make sure that no catastrophic event...might occur."

Yost adds: "Reports to date are that copper processing by IBM and Motorola is all on larger-geometry devices. They're easier to output, because there's more room for errors [and you can] demonstrate reliability aspects and develop better barrier materials."

He pinpoints two potential problems for process engineers. One is the possibility that copper could delaminate from the sidewall in a dual-damascene process and cause "a little crack between the copper and the wall, a killer defect." The other is vias landing "half on the copper and half on the oxide. If you trench into the oxide you get some weird geometries."

"The confinement of copper in metallization and the isolation of copper is very essential to preventing any device and reliability problems," agrees John Ormando, copper program manager at Sematech. "In most cases the defects will get polished off unless they fall into a via or trench. The same thing could happen with barrier seed deposition." Whether they're killer defects or not depends on their size, he says.

"Quite honestly, my point is the copper probe yield is going to be as good as aluminum's. The focus is on the reliability aspects of [copper integration], because that's where everybody is paranoid," Yost notes.

On the matter of defects, the chipmaker leading the copper rush is remaining mum for the moment. IBM will discuss just about everything else about copper, except for defects. "At this point IBM does not want to discuss defectivity issues," replies a disappointed IBM engineer to an interview request. He was willing to talk, but word came down from the corporate level nixing the idea. "Copper is so new. They're treating it as a proprietary issue."

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