INDUSTRY NEWS

Chartered signs copper pact with Lucent and teams with Motorola, H-P in CMOS venture

Abusy Chartered Semiconductor Manufacturing recently signed two joint agreements to develop advanced copper interconnect technology and another to develop a 0.25-µm test chip for IC designers. All three pacts signed by the Singapore wafer foundry are with chipmakers based in the United States.

Chartered and Lucent Technologies will collaborate on developing a common manufacturing process platform using advanced low-k dielectric aluminum and copper interconnects. The research will focus on processes for CMOS devices with geometries of 0.18 and 0.16 µm. Engineers from Lucent and Chartered will work together at Lucent's research facility in Orlando, FL. They will transfer the results of the collaboration to their joint fab in Singapore, a volume manufacturing plant called Silicon Manufacturing Partners (SMP). Both companies may also use the advanced processes in any of their respective fabs.

Calling the venture "significant," Lee Ying Adams, assistant chief executive of the Singapore National Science and Technology Board, says it "will elevate the level of technology capability and expertise in the wafer fab industry in Singapore." The collaboration will shorten the development process, says Adams, and "in the semiconductor industry, fast time-to-market is an important business consideration."

Mark Pinto, CTO of Lucent's Microelectronics Group, notes that the advanced interconnect technologies developed with Chartered will provide a common tool set for both SMP and Lucent's other fabs around the world. "That gives us more flexibility to match manufacturing demand with fab capacity and availability."

The partners will combine the interconnect work with transistor technologies. The resulting processes will be developed for chips used in data communications, mobile communications, graphics, and consumer electronics.

In another alliance, Chartered signed a memorandum of understanding with Motorola and Hewlett-Packard that calls for Motorola to license an advanced CMOS technology to Chartered and Chartered Silicon Partners (CSP), a joint venture with Hewlett-Packard. Chartered and CSP will receive the next three generations of the technology, called HiPerMOS. The research, which includes copper interconnect technology, will begin with 0.15-µm processes.

The arrangement extends existing relationships between Motorola and Hewlett-Packard and Chartered and Hewlett-Packard. It also establishes a new collaboration between Motorola and Chartered. Motorola says the foundry's selection of HiPerMOS technology will help establish the process as an industry standard. The platform is suitable for use with advanced CMOS technology, the chipmaker says. In addition to ensuring a steady supply of wafers from Chartered and CSP, the alliance enables Motorola to provide its DigitalDNA embedded processing products to customers.

The agreement calls for Motorola to receive licensing fees and royalties for the use of the HiPerMOS technology. Hewlett-Packard gets access to advanced process technology and manufacturing. Its components group supplies ASICs to the company's computer, printer, and measurement businesses.

Finally, Chartered and Synopsys of Mountain View, CA, signed an agreement to develop silicon-calibrated technology files for the foundry's 0.25-µm-process clients. The files use Synopsys transistor-level timing and layout extraction tools. Synopsys makes electronic design automation systems.

The two companies are exchanging design information and materials to create a 0.25-µm test chip to validate the tools, models, and test files in actual silicon. Synopsys's Direct Silicon Access Labs develop the layout of the test structure, while Chartered makes the test chip and supplies finished wafers to Synopsys.

The goal of the collaboration is to improve the success rate of deep-submicron designs on first-run silicon, says Chartered executive Ana Hunter. "The collaboration...supports that goal by ensuring that these state-of-the-art tools are silicon verified and tuned to our 0.25-µm processes."

The methodology enables Synopsys to correlate its technology files with Chartered's manufacturing process, notes Larry Yamada, vice president of marketing for Synopsys's EPIC Technology Group. "Designers require fast and accurate analysis as geometries shrink and complexity increases. This [DSA methodology] helps our mutual customers reduce the performance gap by realizing speeds more in line with silicon potential."

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