SURFACE CHEMISTRIES

Enhancing yield through argon/nitrogen cryokinetic aerosol cleaning after via processing

Jeffery W. Butterbaugh, Steve Loper, and Greg Thomes, FSI International; and Dale Sheu, Texas Instruments

As the number of metallization levels in IC manufacturing increases, it becomes more critical to control and reduce defects at each step of the metallization process. Current designs include up to five or more metallization levels. At the same time, critical dimensions are decreasing, making IC yields sensitive to ever-smaller particles. Yield losses because of defects at each metallization level multiply as the number of levels increases, making it increasingly important to identify and eliminate the defects that cause yield loss. The National Technology Roadmap for Semiconductors (NTRS) drives metallization/dielectric defect levels of <0.15/cm² for particles greater than 90 nm for the 180-nm technology node and <0.10/cm² for particles greater than 65 nm for the 130-nm technology node.¹

The process of metallization involves alternating layers of patterned metal and dielectrics with interconnecting passages—vias—patterned in the dielectric layers. To achieve minimum dimensions during via patterning, it is necessary to use plasma chemistries that cause sidewall polymerization. Sidewall polymerization deposits heavy levels of etch residues after photoresist removal. These residues must be removed before the next level of metallization is deposited, but the presence of exposed metal at the bottom of the via opening precludes the use of traditional acids and bases commonly used during transistor fabrication. Dielectric materials also complicate the residue removal process. Spin-on dielectrics are particularly sensitive to water-based cleaning chemistries.

Many techniques using specialty chemistries have been developed and used successfully to remove residues. These techniques effectively attack and remove sidewall residues and polymers from the patterned vias but are often less effective at carrying them away from the wafer surface because of the relatively high viscosity of the specialty chemicals. Chemicals normally used for particle removal during transistor fabrication are not usable at this stage, again because of exposed metal and the use of spin-on dielectrics in the dielectric stack.

This article discusses the use of argon/nitrogen aerosol (cryokinetic) cleaning to remove defects commonly remaining on the wafer surface after via processing. By evaluating cleaning techniques for use on the 0.25-µm production line at Texas Instruments' DMOS 5 fab (Dallas), it was found that cryokinetic cleaning is an effective method for removing via process defects and improving wafer yield.

Cryogenic Aerosol Cleaning

FSI International (Chaska, MN) introduced the argon/nitrogen aerosol cleaning process in its Aries CryoKinetic cleaning system in 1996. This method is a nonchemical, nondamaging process that cleans the wafer surface with thousands of microscopic argon/nitrogen ice crystals.^2,3 Figure 1 is a schematic representation of the Aries system. A mixture of argon and nitrogen gas at approximately 70 psi is precooled to form a liquid/gas mixture. This mixture flows into a tube and is injected through tiny holes into the vacuum chamber. The flow is directed toward the wafer surface. As the liquid/gas mixture is injected into the vacuum chamber, the liquid portion expands and breaks up into small fragments. The small fragments undergo evaporative cooling, which causes them to freeze into solid crystals. These crystals range from less than 0.5 µm to over 5.0 µm and can attain velocities of up to 100 m/sec.

Figure 1: Schematic of the cryokinetic cleaning system.

Contaminants are dislodged from the wafer surface mainly through momentum transfer from the ice crystal to the contaminant particle. Once dislodged, the contaminant particle is carried away from the surface of the wafer by thermophoretic forces and is swept out of the cleaning chamber by a carefully engineered laminar-flow field.^4,5 The ice crystals then undergo sublimation back to gas-phase argon and nitrogen in the exhaust.

The argon/nitrogen aerosol method is particularly suitable for cleaning wafer surfaces during the metallization and interconnect processes. Because it is accomplished with inert gases, this method is safe to use anywhere in the IC production line. Extensive studies of argon/nitrogen cryogenic aerosols have shown that they do not damage or charge wafer surfaces.³

Defect Measurements

Figure 2 presents micrographs of typical defects that were found on the surface of the intermetal dielectric after the baseline via-patterning process sequence (resist patterning, plasma etching, resist ashing, and post-ash solvent cleaning). Defects were composed of silicon oxide or aluminum, which probably resulted from the various sidewall residues deposited during plasma etching. Figure 3 illustrates how the defect shown in Figure 2b evolved into a defect in the subsequent metallization layer. The defect that remained after via patterning was coated with the TiN barrier layer, as shown in Figure 3b. After tungsten deposition and etchback, this defect appeared more like a ridge of material with an open center, as shown in Figure 3c. Finally, Figure 3d illustrates how the defect looked after aluminum metallization and etch. Depending on where this defect falls in the metallization pattern, it is likely to cause an electrical short.

Figure 2: Micrographs showing typical defects remaining on the wafer surface after via patterning, which were composed of (a) silicon dioxide, or (b) aluminum.

Figure 3: Micrographs showing the evolution of an aluminum defect. It was initially present (a) after via patterning and was altered (b) after coating of the defect in the TiN barrier deposition phase, (c) after tungsten deposition and etchback, and (d) after aluminum metallization and etch.

Figure 4 compares surface defect levels (at an approximate resolution of 0.2 µm) with and without aerosol cleaning and before and after the third-level via-etch process. The defect maps showing the sum of 36 wafers from three different lots illustrate the defect reduction achieved by the cryokinetic cleaning process. On average, about 26 defects were detected on each wafer before the third-level via-etch process. After the baseline process, an average of about 29 defects were found on each wafer. The wafers that underwent the aerosol cleaning process had an average of 25 defects on each wafer before third-level via-etch and only 7.8 defects after the baseline process and aerosol cleaning were carried out—a decrease of 69%. The solvent cleaning process was not able to remove many surface defects, whereas the cryokinetic process was highly effective. Some of the defects not removed by the aerosol process were embedded in the dielectric layer, the result of defect formation during the deposition process. These defects caused yield loss in the subsequent metallization level in the form of shorts and opens.

Figure 4: Defect maps showing the sum of defects from 36 wafers out of three split lots. Map ( a) shows the baseline process performance before third-level via etch (average of 26 defects/wafer), and map (b) shows the baseline process performance after via etch (average of 29 defects). Map (c) shows the baseline process with aerosol cleaning before third-level via etch (average of 25 defects), and map (d) shows the baseline process with aerosol cleaning after via etch (average of 7.8 defects).

Yield

Tests were conducted by comparing lots that underwent the argon/nitrogen aerosol cleaning process with lots that underwent the standard cleaning process. First, product lots were removed from the production line, hand carried, and flown from Texas Instruments' DMOS 5 fab to FSI. Then they were split and processed through the Aries cleaning tool in FSI's Class 1 process lab, hand carried, and flown back to Dallas, where they were reinserted into the production line. The metal levels of three- and five-level metal products were investigated. Half of each lot underwent the baseline via-patterning process without cryokinetic aerosol cleaning for all via levels and the other half underwent the same process with aerosol cleaning for all via levels. Figure 5 compares the normalized yield improvement that resulted from both methods.

Figure 5: Test results showing normalized yield improvements for three split lots with three- and five-level metallization.

Figure 6: Electrical defect density data at the final test for a five-level metallization process shows that an average defect density reduction of 0.015/cm² was achieved with aerosol cleaning.

Three lots each of the three- and five-level metal product types were split, for a total of six split lots. For each of the lots, the yield for the aerosol split was normalized to the yield of the baseline split. On average, the three-level metal product experienced a normalized yield improvement of more than 6%, while the five-level product experienced a normalized yield improvement of more than 30%. The main cause of this improvement was a defect reduction in the subsequent metallization layer. Figure 6 depicts the electrically measured defect density for each of the three five-level lots, which showed an average reduction of 0.015 defects/cm². This indicates that the removal of defects reduced the occurrence of electrical shorts and opens in the metal layer deposited over them, which is consistent with the defect evolution shown in Figure 3.

Figure 7: Trend chart showing the significant reduction of in-line TiN barrier defect density (no./cm²) at the second via level after implementing the aerosol process.

After the tool was installed in the production line, a reduction in defect density was clearly noticeable. Figure 7 is a trend chart showing the defect density levels measured after the second-level via-patterning process. The aerosol cleaning process effectively eliminates occasional out-of-control defect levels and reduces the overall baseline defect level. Depending on baseline defect levels, critical dimensions, and the sensitivity of device yield to metallization defects, yield improvements of up to several percentage points can be expected from implementing argon/nitrogen aerosol cleaning after via patterning. Although the economics of semiconductor operations differ, a return on investment should be realized by modestly increasing final chip yield.

Conclusion

Cryokinetic aerosol cleaning has been shown to effectively reduce defects at the via-patterning process step. A reduction in defects at the via levels contributes directly to improving normalized final yield by over 6% for three- and five-level metal products. This yield improvement is mainly due to a reduction in electrical defects in the subsequent metallization layer. Cryokinetic aerosol cleaning is nonreactive, noncorrosive, nondamaging, and environmentally benign. It can be used virtually anywhere in the process line where loosely bound defects are found to cause yield loss.

Acknowledgments

We wish to acknowledge Dave Doucette, formerly with Texas Instruments and now with XFAB Texas, Lubbock, TX, and Joel Barnett and Dave Malis, both of FSI International, whose efforts facilitated the initial live-product split-lot work performed at the FSI applications lab. We also wish to acknowledge TI yield enhancement section manager John P. Campbell, who was instrumental in introducing cryogenic aerosol cleaning to the DMOS 5 production line.

References

1. The National Technology Roadmap for Semiconductor Technology Needs (San Jose: Semiconductor Industry Association, 1997).

2. JJ Wu et al., "Wafer Cleaning with Cryogenic Argon Aerosols," Semiconductor International 19, no. 9 (1996):113—118.

3. JF Weygand et al., "Cleaning Silicon Wafers with an Argon/Nitrogen Cryogenic Aerosol Process," MICRO 15, no. 4 (1997): 47—54.

4. N Narayanswami, "On the Generation of Cryogenic Aerosols for Wafer Processing," Cleaning Technology in Semiconductor Device Manufacturing V, ECS Proceedings 97, no. 35 (1997): 357—364.

5. N Narayanswami, "Thermophoresis Assisted Cryogenic Aerosol Cleaning of Wafers," Cleaning Technology in Semiconductor Device Manufacturing V, ECS Proceedings 97, no. 35 (1997): 350—356.

Jeffery W. Butterbaugh, PhD, is manager of surface conditioning division applications development at FSI International (Chaska, MN). Since joining FSI International in 1993, he has led process development for photochemical wafer cleaning technology, anhydrous HF wafer cleaning, and cryokinetic aerosol wafer cleaning. Butterbaugh is responsible for applications development on all FSI surface conditioning division products. He holds four U.S. patents and has authored or coauthored more than 20 papers on plasma etching and surface conditioning. He received his doctorate in chemical engineering from MIT in 1990 and his BS in chemical engineering from the University of Minnesota (Twin Cities) in 1984. (Butterbaugh can be reached at 612/448-8089 or jbutterbaugh@fsi-intl.com.)

Steve Loper joined FSI International as a field applications engineer in the surface conditioning division in 1998. He has more than 10 years of lab experience in the semiconductor industry, most of which he has spent in wafer processing. He received his BS degree in electrical engineering from the University of Minnesota (Twin Cities) in 1989. (Loper can be reached at 612/361-7314 or steve.loper@fsi-intl.com.)

Greg Thomes is a process engineer in the surface conditioning division at FSI International, where he is responsible for applications development and demonstration on FSI's Aries CryoKinetic surface conditioning system. He has worked in the semiconductor industry for 18 years. He has a BA in biology from St. John's University in Collegeville, MN. (Thomes can be reached at 612/361-8125 or gthomes@fsi-intl.com.)

Dale Sheu is a yield enhancement engineer at Texas Instruments' DMOS 5 fab (Dallas), where he is responsible for introducing automatic defect classification into the manufacturing line. He has worked at TI for four years in yield enhancement and diffusion. Sheu graduated with a BS degree in chemical engineering from the University of Arizona (Tucson) in 1992 and received his MS in chemical engineering from New Mexico State University Las Cruces in 1995. (Sheu can be reached at 972/927-7672 or d-sheu1@ti.com.)

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