Preventing cross-contamination caused by copper diffusion and other sources
Ted Cacouris, Novellus Systems
The semiconductor industry's introduction of copper into the manufacturing process raises some important issues concerning copper contamination.
Several key developments have fostered the transition from aluminum to copper interconnects: damascene processing to surmount the difficulties in etching copper; copper electrofill technology allowing a low-cost, bottom-up fill of damascene features; and the deployment of new materials and methods that avoid the catastrophic contamination of devices. To prevent device contamination caused by copper diffusion from interconnects into the silicon, diffusion barriers such as silicon nitride and tantalum or tantalum nitride have been created.
Preventing contamination caused by copper diffusion from the inadvertent deposition of copper on wafer backsides poses a more daunting challenge. This problem has been addressed in part by more stringent requirements imposed on processing equipment and more demanding protocols imposed on manufacturing practices. The transition to copper is reminiscent of the earlier introduction of chemical-mechanical planarization into semiconductor manufacturing, whereby tools were initially segregated in separate, isolated areas for fear that slurry could contaminate the entire fab. This article investigates the issues raised by the semiconductor industry's introduction of copper into the manufacturing process and discusses methods such as equipment segregation, dedicated tools, and special wafer-handling methods that help prevent copper contamination.
Effects of Copper Contamination
Copper diffusion in silicon devices can lead to two main types of failures: the deterioration of insulators at the interconnect levels, leading to shorts or leaky paths between conductors; and, because copper is a deep-level trap in the silicon bandgap, high standby leakage of transistors, leading to inoperability.13 As illustrated in Figure 1, under moderate temperatures atomic copper diffuses rapidly in silicon, having a higher diffusion coefficient in silicon than gold, silver, sodium, and iron.4 And under moderate temperatures and bias conditions, ionic copper is a fast diffuser in many dielectric materials. As a result, any trace copper that finds its way either into silicon directly or into a dielectric can have detrimental effects. Because the initial market for copper products is occupied by high-end logic devices, a trace amount of copper in unwanted places can have a severe financial impact200-mm wafers populated with $300 logic chips represent a potential revenue of $60,000 per wafer.
Figure 1: Diagram of a test for barrier effectiveness using blanket films in which a thin CVD titanium nitride barrier, sandwiched between copper and silicon, breaks down at 600°C, leaving a pitted silicon surface.
For this reason, manufacturing plants have been reluctant to make the transition to copper and have done so only after extensive preparations. Stringent requirements have been placed on equipment suppliers to ensure that no detectable traces of copper are present on the bevels and backsides of wafers after processing. New factory protocols have been developed to heighten awareness among production personnel and to contain copper contamination. For example, copper personnel in several U.S. fabs wear distinctively colored cleanroom gowns so that they can be prevented from entering noncopper stations and to remind them to follow copper-specific protocols.
Factory layout can also be used to minimize opportunities for cross-contamination. Several facilities in Europe and Taiwan have been constructed with this precaution in mind. In order to clearly identify the wafers that have received copper processing, specially colored wafer carriers and conspicuous labels indicating the presence of copper products are used to segregate wafers made of different materials. Protocols require that once a wafer has entered a copper bay, it cannot return to a noncopper bay.
Sources of Copper Contamination
Contamination can arise from tools and equipment involved in the deposition and handling of wafers. For example, a deposition tool that coats wafers with copper films may deposit copper on the bevel of the wafer. This wafer may then be sent to a metrology tool equipped with a wafer handler that manipulates the edges of wafers processed in various areas of the fab. This wafer handler, contaminated with copper, can then cross-contaminate wafers that are destined for an etch tool. The etcher eventually becomes contaminated with copper, and the copper "virus" spreads quickly through the fab, accumulating in plasma process chambers, wet benches, and lithography steppers. Contamination can also spread by way of the wafer's backside. Many wafer handlers, or robots, grab or lift wafers by their backsides. Even submonolayer impurity levels of <1015 atoms/cm2 on wafer backsides can result in the increasing contamination of a multipurpose handler such as that used on an in-line scanning electron microscope (SEM).
Figure 2: Dielectric (silicon nitride) and metal (tantalum nitride) barriers encapsulate copper
in a damascene structure and protect against copper migration from interconnect structures to neighboring dielectrics and silicon.
The damascene or dual-damascene process affords devices a certain measure of protection against copper contamination. Copper diffusion barriers such as tantalum nitride, titanium nitride, and insulating silicon nitride provide on-chip protection against copper migration from interconnect structures to neighboring dielectrics and silicon.5 These materials are widely used in the copper damascene process architecture, effectively encapsulating every single interconnect, as illustrated in Figure 2. Frontside layers and processes, however, do not sufficiently protect devices against external sources of copper that may contaminate the bevel and backside regions of the wafer.
The use of dedicated metrology tools for copper processing can also help prevent cross-contamination. However, this can be very costly, especially when defect tools are involved. Since the acquisition of a complete set of copper-dedicated metrology tools can be cost-prohibitive, alternative solutions must be sought. A common approach is to set specifications for all copper tools that limit the detectable levels of copper contamination on wafer backsides. This places the burden of cleanliness on the equipment suppliers.
Critical Cross-Contamination in the Fab
Cassette/Wafer Handling. Wafer handling is the most likely source of copper cross-contamination, since it is the most universal mechanism in a facility. This includes not only automation equipment, such as robots, but also plastic wafer carriers, or cassettes. If copper is left on the wafer bevel as it exits a process tool, the carrier will invariably be contaminated with copper. Great care must be taken either to limit the use of wafer carriers to a specified area or to switch to clean carriers once the copper is removed from the bevel. The management of this task can be logistically complex, because most semiconductor equipment is designed for cassette-to-cassette automationthat is, one carrier handles both incoming and outgoing wafers. Additional costs may be incurred to clean wafer carriers more frequently than otherwise required for particle control.
Shared Metrology Tools. Many fabs view metrology as a non-value-added stepthat is, a necessary evil. Because new metrology equipment is increasingly sophisticated and hence costly, excess capacity and redundancies are rare in this area. For this reason, the metrology area is a prime source of copper contamination. Shared metrology tools may include in-line SEMs for critical dimension measurements, film-thickness monitors, in-line electrical testing equipment, and optical defect inspection devices. Manufacturers generally find that the acquisition of dedicated equipment for copper processing is cost-prohibitive, but they must seek to strike a balance in order to limit the danger of copper cross-contamination.
Lithography. Like metrology tools, lithography tools (steppers, resist tracks, develop tracks) are so expensive that they are often designed as the rate-limiting step in the throughput models of fabs. Such tools are usually "qualified" so that they can be used interchangeably for many mask layers, allowing the dynamic balancing of capacity and redundancy in the event of a tool failure. It is thus difficult to dedicate certain lithography tools for copper interconnect layers.
Wafer Breakage. No factory is immune to wafer breakage, although incidence levels have been decreased dramatically. However, protocols for cleaning tools and areas in which a wafer containing copper films has broken are crucial to preventing factorywide cross-contamination. A decontamination plan understood by all factory personnel is required for each area and tool. Such a plan must assume that the broken copper wafer has contaminated the immediate area in which the breakage occurred, mandating appropriate cleaning methods and wipedowns to remove all traces of copper contamination. For example, if a wafer breaks within a physical vapor deposition (PVD) tool, the tool must be vented and cleaned so that every surface which comes into contact with a wafer either directly or indirectly is copper-free. Unfortunately, no easy test exists for demonstrating the cleanliness of a tool short of analyzing a test wafer for copper contamination.
Tools and Contamination Control
Metrics for copper contamination are usually based on particle adders and trace copper impurities on wafer backsides. Most conservative fabs place such impurity levels at below 1011 atoms/cm2. Measurement methods such as total
x-ray fluorescence (TXRF), vapor phase desorption (VPD), and secondary ion mass spectroscopy (SIMS) can resolve contaminants approaching 109 atoms/cm2. However, a wide variance in measured surface impurities is typically observed when sampling virgin wafers. The establishment of a proper contamination threshold takes this variance into consideration. One fab in Taiwan has applied such a data-driven approach in setting contamination limits. In this facility many robotic wafer handlers are metallic by design and can therefore impart some metal contamination to the wafer through physical contact. To determine the level of copper contamination, TXRF or SIMS is used to sample and measure the backsides of product wafers from the Al(Cu) interconnect manufacturing line. Tests have shown that the equipment contaminates wafers with copper levels as high as 1012 atoms/cm2, leading the facility to establish a copper contamination specification of ¾1012 atoms/cm2.
Copper seed deposition (typically by a PVD technique), copper bulk fill by electroplating, copper CMP, and any associated cleaning steps directly influence copper contamination. Through contact with a PVD tool, for example, a wafer backside can receive trace copper if the PVD copper module does not clamp and physically prevent copper from migrating to the back of the wafer during the deposition step. Also, any target- or shield-generated particles made of copper can find their way to the wafer pedestal or chuck, thereby leading to contamination of the wafer backside. CVD copper deposition is particularly vulnerable to this form of cross-contamination. Any trace copper precursor that does not get pumped away before the wafer is lifted from the heated pedestal results in finite levels of copper deposition on the pedestal, which in turn contaminates wafers.
Figure 3: Bevel region of a wafer lacking barrier material under some areas of the copper
Postplating anneals commonly used to stabilize copper films before the CMP step are another typical mode of copper contamination. Any copper on the wafer lacking an underlying barrier layer to prevent copper diffusion is likely to adversely affect devices, since copper is very mobile at elevated temperatures. For example, when copper is deposited on the entire face of the wafer to maximize the usable diameter (full-face coverage), it wraps over the bevel region. Although an underlying barrier material such as tantalum nitride would otherwise prevent copper diffusion, this barrier may not wrap over the bevel region as extensively as the copper layer, leaving areas exposed to copper diffusion, as illustrated in Figure 3.
Etching tools that define damascene structures are also vulnerable to copper contamination. As a via is etched to open a contact to an underlying copper interconnect, the plasma etch process briefly bombards exposed copper. If care is not taken to design an etch process that does not resputter copper, copper can accumulate over time in the etch chamber, which can in turn contaminate future wafers. Similarly, dielectric tools that are used to cap copper after a copper CMP step such as silicon nitride deposition can cause contamination if care is not taken in handling wafers with exposed copper that enter this module.
Controlling Bevel and Backside Contamination
Copper deposition by means of electroplating can contaminate wafers if copper-containing chemicals are not prevented from reaching a wafer's bevel and backside. These surfaces can be protected by clamping and sealing the wafer hermetically during the plating operation so that only the face of the wafer, not the bevel and backside, is exposed to the process as required. The Sabre Electrofill tool from Novellus Systems (San Jose) has successfully implemented such a method. By using a clamping method known as a clamshell, the tool prevents wafers from being exposed to copper-containing solutions, resulting in wafers whose backsides are free of copper.
Figure 4: TXRF measurements revealing that wafers processed with the clamshell method have a
lower average level and smaller spread of copper contamination than those processed with the wafer backside exposed.
Although contaminated wafers can be cleaned by using aggressive chemical and mechanical techniques, these methods are not as effective as simply avoiding contamination (exposure) in the first place. Furthermore, such cleaning methods can be costly and risky. Figure 4, summarizing the results of a controlled experiment, demonstrates the advantage of protecting the wafer backside. In this example, some wafers were processed with the Sabre process and others with a more conventional approach involving the exposure of wafer backsides to plating solution mists. TXRF measurements revealed that wafers processed with the tool's clamshell method have a lower average level and smaller spread of copper contamination than those processed without the clamshell method. Removing a high level of contamination mandates that a separate step be incorporated into the process flow to clean the wafers immediately after deposition, increasing processing costs.
Figure 5: Copper contamination levels on the backsides of more than 100,000 wafers processed
with the clamshell method were <1011 atoms/cm2.
An extensive set of TXRF data, shown in Figure 5, was collected by IBM over a period of time when more than 100,000 wafers were processed through a Sabre tool. Silicon test wafers were periodically sampled during production by loading them upside down in the tool so that the wafer face came into contact with the clamping surfaces. Then they were run through a typical process sequence. A subsequent TXRF surface analysis showed a consistent copper concentration of <1011 atoms/cm2, which was similar to the copper concentration on control wafers that did not undergo the plating process.
Copper contamination presents a significant challenge to the production of on-chip copper interconnects. A thorough grasp of the potential sources of contamination has led manufacturers to develop copper-specific methods that are not only conservative but also costly. Equipment segregation, dedicated equipment such as metrology tools, and novel wafer-handling methods help prevent cross-contamination. Further refinements in copper-processing tools will ultimately greatly lessen the risk of cross-contamination, easing the transition to high-volume copper manufacturing.
The author would like to acknowledge the valuable contributions of Eliot Broadbent and Michal Danek of Novellus Systems in the preparation of this article.
1. AG Milnes, Deep Impurities in Semiconductors (New York: Wiley, 1973).
2. RN Hall and JH Racette, "Diffusion and Solubility of Copper in Extrinsic and Intrinsic Germanium, Silicon, and Gallium Arsenide," Journal of Applied Physics 35, no.3 (1964): 379385.
3. EM Conwell, "Properties of Silicon and Germanium, Part II," in Proceedings of the IRE 46, no. 11 (New York: Institute of Reliability Engineering, 1958), 12811283.
4. DL Kendall and DB DeVries, "Diffusion in Silicon," in Semiconductor Silicon, eds. RR Haberecht and EL Kern (New York: Electrochemical Society, 1969), 358371.
5. K Holloway et al., "Tantalum as a Diffusion Barrier between Cooper and Silicon: Failure Mechanism and Effect of Nitrogen Additions," Journal of Applied Physics 71, no.11 (1992): 54335444.
Ted Cacouris, PhD, is a senior technologist for the copper damascene program at the Novellus Portland Technology Center (Portland, OR). In 1990 he joined IBM, where he evaluated several techniques for copper deposition, optimizing barriers, and seed layers for electroplating. This work culminated in the integration of copper interconnects and low-k films. Cacouris joined Intel in 1993 as a member of the process integration team for the development and manufacturing of Pentium microprocessors and moved on to Novellus Systems in 1996 as a member of the new Portland Technology Center startup team. Cacouris belongs to the Institute of Electrical and Electronics Engineers and the Materials Research Society. He received his PhD in electrical engineering from Columbia University (New York City) in 1990. (Cacouris can be reached at 503/685-8366 or firstname.lastname@example.org.)
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