INDUSTRY NEWS

SEZ, AlliedSignal, Rodel are latest firms to pursue CMP alternatives

SEZ America and AlliedSignal have joined the ranks of companies looking for a kinder, gentler alternative to the rigors of CMP for manufacturing the next generation of semiconductors. The two firms have formed an alliance to develop planarization alternatives for low-k materials, whose porosity makes them especially fragile. AlliedSignal's electronic materials (ASEM) division will develop ultraclean chemistries for use in SEZ's spin-process equipment. Ideally, the process will remove copper films without damaging the low-k materials.

The partners claim the process will help chipmakers improve both yields and fab productivity. SEZ also plans to introduce several new platforms for frontside wafer processes in devices with 0.18-µm geometries and below. AlliedSignal has begun working with an SEZ 203 spin processor with a 200-mm wafer platform at the ASEM low-k R&D facility in Sunnyvale, CA.

No Grind: Using this spin processor and special chemicals, SEZ hopes to develop a film-etchback alternative to traditional CMP. Photo coutrtesy of Sez America

SEZ and ASEM are on that growing list of companies looking for planarization substitutes. At 0.35-µm linewidths, spin-on-glass, for example, "hit a brick wall," asserts Kevin Witt, interconnect program manager for Rodel, a major supplier to the polisher market. In early July, Rodel and SpeedFam-IPEC agreed to collaborate on research for CMP processes using slurry-free products from 3M. Their initial collaboration will focus on two areas, copper processes using IPEC's 676 and 776 platforms and shallow trench isolation (STI) processes using a new web platform from SpeedFam-IPEC.

The shift toward the use of copper and low-k dielectric materials in next-generation chips presents some yield problems for the CMP process, which, most acknowledge, has matured to the point where process engineers can now sleep soundly at night.

"From a yield standpoint the key point of this application is to focus on not inducing mechanical stresses on the low-k itself," says Michael West, SEZ's business and strategic technology director. "Allied was given the task of coming up with a turnkey application where its low-k porous material could be subsequently planarized or etched back and not damage that spongelike material. That's where SEZ comes in on the yield issue.

"We introduce no mechanical damage. There are no 'crushing' aspects, if you will . . . and there's no requirement for subsequent cleanup. People hate it when we say this, but there is a contamination aspect [to the use of] slurry and CMP itself. In theory, that's where the yield enhancement comes from--avoiding contamination and then not damaging the device."

West's counterpart at ASEM agrees, with a slight reservation. "There's an inherent problem removing particles during the CMP process," says Lynn Forester, director of strategic technology development and business alliances. "Most people have dealt with that just fine. I wouldn't say it's a problem [with the state of the art in CMP]." However, she points out, "each time you develop a new process you have to do that again and again to make sure it's sufficiently clean." If they succeed, SEZ and ASEM would offer chipmakers the advantage of a chemical-etch planarization process with no grinding involved. "You'd just have liquids. And liquids can be filtered down to the 0.1-µm [impurity] level. You'd have an inherent cleanliness advantage," Forester explains.

An added benefit is that there's "no drying issue. At some point the wafer will dry and be just fine," Forester says. "That's the hope for this process, and the development is just beginning. That would be one of the potential advantages. At this point we'd still need to do a lot of work on actual particle measurement."

Robert Castellano is president of the Information Network, a market research firm based in New Tripoli, PA, which closely monitors CMP trends. He stresses that Japanese chipmakers are still using "alternative types of technology" to planarize wafers, including oxide reflow, or spin-on-glass. "Not everybody is necessarily going to the use of CMP. Some are trying to tweak their technology."

Problems arise at the smaller feature sizes, he notes. Those problems create opportunities for endeavors such as the one pursued by SEZ and ASEM as the companies try to extend the capabilities of their existing tools and materials. SEZ already has the "technology for spinning the wafers," Castellano points out, and needs merely to incorporate the proper chemistries, if possible.

"With any new type of technology coming into play you're going to have lower yields until things start ramping up [and the] technology more or less works its way into the mainstream." Chipmakers working with low-k material and copper "are getting some very low yields as far as their processing is concerned. Some of this has to do with the fact that copper is softer [than aluminum]. You tend to get scratching and dishing. New pads need to be developed."

Low-k film is not as resilient as a silicon dioxide film, and "this fragility of the new materials opens up an opportunity for SEZ to just extend its existing planarization tools to CMP. It's nothing necessarily new. AlliedSignal is working with them to develop new types of polymers. The whole thing boils down to buzzwords." The mystique surrounding copper and low-k in the marketplace, asserts Castellano, allows vendors to attach those terms to a tool and call it a "copper" system, for example, when it can also be used for aluminum-based processes.

West says SEZ has little or no competition for its technology, which may give the company and ASEM a good shot at successfully launching their venture in a growing copper-based processing environment. Extrapolating from the present tungsten or oxide CMP markets, he sees a "market greater than what it is today, if for no other reason than the stack sizes are going up from five or six or seven layers of metal to eight. The answer [to the market-size question] is in the billions of dollars. With copper being the up-and-coming process, we decided to get on the wave and ride it from the beginning."

Although the size of the CMP market has abated somewhat, that wave could prove to be a tsunami. Market researcher Castellano says the worldwide market for CMP polishers will grow from $551 million in 1998 to $629 million in 1999 on its way to $1.34 billion in 2003, a compound annual growth rate of 19.4%.

Ron Dornseif, a principal analyst with Dataquest, says that overall the polisher market is "not necessarily the fastest growing in terms of compound annual growth rate because the equipment segment is five years old." Yet, it is still one of the highest-growth segments, says Dornseif, who foresees a CMP equipment market "in excess of $1.9 billion in 2004."

No Slurry: Rodel is working with SpeedFam-IPEC on a CMP alternative using this slurry-free polishing matrix from 3M. Photo coutrtesy of Rodel

In terms of market share, market leader Applied Materials had sales of $207 million in 1998 and second-place Ebara took in $179 million, according to Castellano. SpeedFam and IPEC, not having merged yet in 1998, had sales of $27 million and $82 million, respectively, for a combined market share of $109 million. Strasbaugh followed at approximately $40 million. "Everybody else was in the noise at around $10 million annually," says the analyst.

Earlier this year, Applied agreed to buy Obsidian, a firm that specializes in a "slurryless" planarization method. The fixed abrasive-pad technology "is relatively old," says Castellano. The analyst says the "word I got on the street" is that Intel was making a list of tool companies they were interested in as the microprocessor giant contemplated the joy of producing 0.18-µm chips in volume. Applied will incorporate the technology with its Mirra polisher, using its global marketing and service muscle and broad product sweep to offer customers "a complete suite of tools. You can do a lot of manipulations in terms of selling price."

Slurry-free planarization has definite allure for chipmakers, Castellano believes. "One of the things about this slurry business is it's not just the slurry you have to be concerned about. It costs $600 or so for a 55-gallon container. One of the problems with [slurry] is that you have to go through elaborate cleaning techniques; you also have to pipe it in, you have to dispose of it, and then there's all the DI water you have to use. If you could get rid of that slurry," the market researcher continues, "semiconductor companies could save a lot of money. It's the whole slurry infrastructure that will minimize the cost of doing CMP. This is why Intel was looking at it so carefully, Sony has a slurryless pad, SpeedFam-IPEC is making a tool, and others are looking at it. Rodel is marketing a tool with 3M. The company is the second-place player in the slurry business, and if the tool does take off, it's a win-win [proposition] for them."

Joan Koppenbrink, Rodel's vice president of corporate marketing, says the company is "very encouraged" by the results of its alliance with 3M, noting there is "definitely a high amount of interest" among Rodel's customer base. Witt, Koppenbrink's colleague, says customers in Asia, Europe, and the United States are using the technology. Without elaborating further, he says clients are using the technology to make memory chips and other devices with linewidths "at 0.25 µm and below." Others are developing next-generation products, what Witt calls "their skunk-work projects.

"What it really comes down to is it makes the process much more 'manufacturable' and capable, and it gives you a lot of opportunities with shallow trench isolation and copper. We've reached the limitations of spin-on-glass and things like that. That's not an avenue any longer. There might be a few folks with a lower-temperature reflow process or an organic solvent," but Witt sounds skeptical.

Now, partners such as SEZ and ASEM are in a three-legged race to get to the copper finish line ahead of possible competitors. "We want to make sure we're in time for what would have been the 0.15-µm technology node until they took it out of the [ITRS] roadmap," says Forester of ASEM with a laugh. "That's our goal--to be on time. Someone's going to build a 300-mm fab."

SEZ and ASEM are splitting the developmental costs for the low-k planarization alternatives. Neither Forester nor West would say how much the companies will spend on the project, which West says is "relatively open ended" and could last for "the next two to three years." The partners "hope to have publishable primary data by the end of the first quarter in 2000," he adds. Their tool will offer a throughput of at least 40 wafers per hour"and will be absolutely competitive."

Will this technology offer an alternative to the Applieds and Lams of the world then? "We hope it's an alternative," asserts Forester. At this point it's really a developmental [matter]. . . . There are a lot of possibilities it won't work and won't have the uniformity required. But the uniformities we've achieved on some experimental results have been very good and would lead us to believe we should continue. The wafer costs are going to be significant, however. You need patterned 200-mm wafers. You can do only so much on blanks."

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