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Building Copperopolis

Technical articles from equipment and materials suppliers as well as from the research and chipmaker communities.

(Building Copperopolis II) Reducing edge and bevel contamination to help enhance copper process yields
A side-selectable wet processing chamber shows promise as a method for removing wafer backside contamination and eliminating copper films on the bevel and edge of the wafer. (October 2000)

(Building Copperopolis II) Developing a defect reduction strategy for the copper dual-damascene oxide etch process
In a new defect reduction strategy, patterned wafers replace bare silicon wafers to perform line monitoring and detect particles responsible for yield loss on copper production wafers. (July 2000)

(Building Copperopolis II) Using optical metrology to monitor low-k dielectric thin films
Because controlling curing temperature and time is critical for producing high-quality spin-on dielectric thin films, rapid feedback from metrology tests on thermal process tools is needed to correct tool drift . (May 2000)

(Building Copperopolis II) Evaluating wafer reclaim techniques in emerging copper processes
All wafer reclaim companies must address the issue of copper removal while protecting their current processes from copper contamination. (March 2000)

(Building Copperopolis II) Using a wafer backside spin process to eliminate contamination in copper applications
A spin-process technique prevents back-surface particle contamination of the process chuck, creates an edge exclusion zone, and optimizes the copper/barrier material interface. (Jan 2000)

(Building Copperopolis) Enabling low-k material integration through low-ion plasma dry strip processes
Postdielectric dry strip and residue removal are critical steps toward integrating low-k dielectrics into damascene or dual-damascene processes. (Oct '99)

(Building Copperopolis) Treating wastes generated by copper electroplating tools
A copper recovery system recovers up to 99.99% of total copper from spent plating baths and rinsewater from wafer-plating operations, transforming wastes into high-quality metal. (Sept '99)

(Building Copperopolis) Preventing cross-contamination caused by copper diffusion and other sources
Investigates the issues raised by the semiconductor industry's introduction of copper into the manufacturing process and discusses methods such as equipment segregation, dedicated tools, and special wafer-handling methods that help prevent copper contamination. (July '99)

(Building Copperopolis) Implementing SMIF and auto ID to ensure high-volume copper processing integrity
As chip making becomes more automated and copper processing relies more on automation software and automated tools, SMIF and auto ID can be integrated into tool automation systems. (May '99)

(Building Copperopolis) Using TOF-SIMS to inspect copper-patterned wafers for metal contamination
A highly versatile and ultrasensitive technique, TOF-SIMS can be used to analyze samples in the 0.5–500-µm size range on a patterned wafer. (March '99)

(Building Copperopolis) Investigating CMP and post-CMP cleaning issues for dual-damascene copper technology
Discusses the importance of tailoring CMP slurries to the characteristics of copper and tantalum-based barrier materials and describes the capabilities required in post-CMP cleaning formulations. (Jan '99)

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