A regular series of device-level process analyses, written exclusively for MICRO by Chipworks' senior technology adviser, Dick James.
TSMC fabbed Matrix 3-D memory array with unique 0.15-
μm, seven-metal process
Infineon uses vertical structure to optimize on-resistance in power MOS devices
Fujifilm Maximizes Charge-Coupled Device’s 0.35-µm, Two-Metal, Double-Poly Process
Texas Instruments Pushes MEMS Envelope with Micromirror-Based DLP
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