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With device geometries shrinking well into the nanoscale realm, the challenges faced in the transistor formation portion of wafer processing have increased enormously. This series focuses on such front-end-of-line processes and challenges as strain engineering (sSi, sSO1, etc.), gate stack engineering, nonplanar transistor structures, atomic layer deposition, nondamaging surface preparation and cleaning approaches, and advanced metrology and inspection strategies.

Using an STI gap-fill technology with a high-aspect ratio process for 45-nm CMOS and beyond
(June 2006)

Developing a systematic approach to metal gates and high-k dielectrics in future-generation CMOS
(May 2006)

Optimizing the poly1 doping process to reduce deep-trench resistance and leakage
(April 2006)

Meeting the future challenges of high-k gate dielectrics and metal gates
(March 2006)

Accelerating Flash Product Inspections Using a Novel E-beam Inspection Method
(January/February 2006)

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